Datasheet AD7175-2 (Analog Devices) - 58
| Manufacturer | Analog Devices |
| Description | 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers |
| Pages / Page | 63 / 58 — ID REGISTER. Address: 0x07, Reset: 0x0CDX, Name: ID. Table 32. Bit … |
| Revision | B |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ID REGISTER. Address: 0x07, Reset: 0x0CDX, Name: ID. Table 32. Bit Descriptions for ID Bits. Bit Name. Settings. Description. Reset
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Data Sheet AD7175-2
ID REGISTER Address: 0x07, Reset: 0x0CDX, Name: ID
The ID register returns a 16-bit ID. For the AD7175-2, this must be 0x0CDX.
Table 32. Bit Descriptions for ID Bits Bit Name Settings Description Reset Access
[15:0] ID The ID register returns a 16-bit ID code that is specific to the ADC. 0x0CDX R 0x0CDX AD7175-2.
CHANNEL REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CH0
The channel registers are 16-bit registers that select which channels are currently active, which inputs are selected for each channel, and which setup configures the ADC for that channel.
Table 33. Bit Descriptions for CH0 Bits Bit Name Settings Description Reset Access
15 CH_EN0 This bit enables Channel 0. If more than one channel is enabled, the ADC 0x1 RW automatically sequences between them. 0 Disabled. 1 Enabled (default). 14 RESERVED This bit is reserved; set this bit to 0. 0x0 R [13:12] SETUP_SEL0 These bits identify which of the four setups configure the ADC for this 0x0 RW channel. A setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, and gain register. All channels can use the same setup, in which case the same 2-bit value must be written to these bits on all active channels, or up to four channels can be configured differently. 00 Setup 0. 01 Setup 1. 10 Setup 2. 11 Setup 3. [11:10] RESERVED These bits are reserved; set these bits to 0. 0x0 R [9:5] AINPOS0 These bits select which input is connected to the positive input of the 0x0 RW ADC for this channel. 00000 AIN0 (default). 00001 AIN1. 00010 AIN2. 00011 AIN3. 00100 AIN4. 10001 Temperature sensor+. 10010 Temperature sensor−. 10011 ((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled). 10100 ((AVDD1 − AVSS)/5)− (analog input buffers must be enabled). 10101 REF+. 10110 REF−. Rev. B | Page 57 of 62
ID REGISTER Address: 0x07, Reset: 0x0CDX, Name: ID
The ID register returns a 16-bit ID. For the AD7175-2, this must be 0x0CDX.
Table 32. Bit Descriptions for ID Bits Bit Name Settings Description Reset Access
[15:0] ID The ID register returns a 16-bit ID code that is specific to the ADC. 0x0CDX R 0x0CDX AD7175-2.
CHANNEL REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CH0
The channel registers are 16-bit registers that select which channels are currently active, which inputs are selected for each channel, and which setup configures the ADC for that channel.
Table 33. Bit Descriptions for CH0 Bits Bit Name Settings Description Reset Access
15 CH_EN0 This bit enables Channel 0. If more than one channel is enabled, the ADC 0x1 RW automatically sequences between them. 0 Disabled. 1 Enabled (default). 14 RESERVED This bit is reserved; set this bit to 0. 0x0 R [13:12] SETUP_SEL0 These bits identify which of the four setups configure the ADC for this 0x0 RW channel. A setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, and gain register. All channels can use the same setup, in which case the same 2-bit value must be written to these bits on all active channels, or up to four channels can be configured differently. 00 Setup 0. 01 Setup 1. 10 Setup 2. 11 Setup 3. [11:10] RESERVED These bits are reserved; set these bits to 0. 0x0 R [9:5] AINPOS0 These bits select which input is connected to the positive input of the 0x0 RW ADC for this channel. 00000 AIN0 (default). 00001 AIN1. 00010 AIN2. 00011 AIN3. 00100 AIN4. 10001 Temperature sensor+. 10010 Temperature sensor−. 10011 ((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled). 10100 ((AVDD1 − AVSS)/5)− (analog input buffers must be enabled). 10101 REF+. 10110 REF−. Rev. B | Page 57 of 62