Datasheet AD9635 (Analog Devices) - 17

AD9635 Data Sheet 120 110 100 100 SFDRFS SFDR 90 80 80 SNRFS Bc) Bc) /d /d 70 S S SNR 60 BF BF d d 60 SFDR DR ( DR ( 50 F 40 F S S SNR 40 NR/ NR/ S 20 S 30 20 0 10 –20 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
032
0 20 40 60 80 100 120 140 160 180 200 220 240 260
035
INPUT AMPLITUDE (dBFS)
10577-
INPUT FREQUENCY (MHz)
10577- Figure 32. SNR/SFDR vs. Analog Input Level; fIN = 9.7 MHz, fSAMPLE = 125 MSPS Figure 35. SNR/SFDR vs. fIN; fSAMPLE = 125 MSPS
0 120 AIN1 AND AIN2 = –7dBFS 110 SFDR = 89.1dBc –20 IMD2 = –93.9dBc 100 SFDR IMD3 = –91.6dBc 90 –40 S) Bc) 80 F B /d S –60 70 E (d BF SNR D d 60 U IT –80 DR ( F 50 S MPL A 40 NR/ –100 S 30 20 –120 10 –140 0 0 20 40 60
033
–40 –20 0 20 40 60 80
071
FREQUENCY (MHz)
10577-
TEMPERATURE (°C)
10577- Figure 33. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, Figure 36. SNR/SFDR vs. Temperature; fIN = 9.7 MHz, fSAMPLE = 125 MSPS fSAMPLE = 125 MSPS
0 0.4 0.3 –20 SFDR (dBc) 0.2 ) S –40 BF d 0.1 ) Bc/ IMD3 (dBc) B d –60 LS 0 D3 ( L ( IM IN –0.1 DR/ –80 F S SFDR (dBFS) –0.2 –100 –0.3 IMD3 (dBFS) –120 –0.4 –90 –70 –50 –30 –10
034
1 343 685 INPUT AMPLITUDE (dBFS) 1027 1369 1711 2053 2395 2737 3079 3421 3763 4105
072 10577-
OUTPUT CODE
10577- Figure 34. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 37. INL; fIN = 9.7 MHz, fSAMPLE = 125 MSPS fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS Rev. B | Page 16 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9635-80 AD9635-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE