Datasheet AD9268 (Analog Devices) - 36

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AD9268 SERIAL PORT INTERFACE (SPI)
The AD9268 serial port interface (SPI) allows the user to configure The falling edge of the CSB, in conjunction with the rising edge the converter for specific functions or operations through a of the SCLK, determines the start of the framing. An example of structured register space provided inside the ADC. The SPI the serial timing and its definitions can be found in Figure 84 gives the user added flexibility and customization, depending on and Table 5. the application. Addresses are accessed via the serial port and Other modes involving the CSB are available. When the CSB is can be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device, into bytes that can be further divided into fields, which are docu- this is called streaming. The CSB can stall high between bytes to mented in the Memory Map section. For detailed operational allow for additional external timing. When CSB is tied high, SPI information, see the AN-877 Application Note, Interfacing to functions are placed in high impedance mode. This mode turns High Speed ADCs via SPI. on any SPI pin secondary functions.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: the SCLK/DFS pin, the Data follows the instruction phase, and its length is determined SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS by the W0 and W1 bits. (a serial clock) is used to synchronize the read and write data In addition to word length, the instruction phase determines presented from and to the ADC. The SDIO/DCS (serial data whether the serial frame is a read or write operation, allowing input/output) is a dual-purpose pin that allows data to be sent the serial port to be used both to program the chip and to read to and read from the internal ADC memory map registers. The the contents of the on-chip memory. The first bit of the first byte in CSB (chip select bar) is an active-low control that enables or a multibyte serial data transfer frame indicates whether a read disables the read and write cycles. command or a write command is issued. If the instruction is a
Table 14. Serial Port Interface Pins
readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to
Pin Function
an output at the appropriate point in the serial frame. SCLK Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. All data is composed of 8-bit words. Data can be sent in MSB-first SDIO Serial Data Input/Output. A dual-purpose pin that mode or in LSB-first mode. MSB first is the default on power-up typically serves as an input or an output, depending on and can be changed via the SPI port configuration register. For the instruction being sent and the relative position in the more information about this and other features, see the AN-877 timing frame. Application Note, Interfacing to High Speed ADCs via SPI. CSB Chip Select Bar. An active-low control that gates the read and write cycles.
t t HIGH DS tCLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE
052
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
3- 0812 Figure 84. Serial Port Interface Timing Diagram Rev. A | Page 35 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE