Datasheet AD6640 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Multi-Channel, Multi-Mode Receiver Chipset |
| Pages / Page | 25 / 8 — Equivalent Circuits–AD6640. AIN. ANALOG. INPUTS. N + 1. ENCODE INPUTS. … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Equivalent Circuits–AD6640. AIN. ANALOG. INPUTS. N + 1. ENCODE INPUTS. (ENCODE). DIGITAL OUTPUTS. N – 2. N – 1. (D11–D0). tOD. VCH AVCC. DVCC. BUF
Model Line for this Datasheet
Text Version of Document
Equivalent Circuits–AD6640 tA AIN N ANALOG INPUTS N + 1 AIN ENCODE INPUTS (ENCODE) DIGITAL OUTPUTS N – 2 N – 1 N (D11–D0) tOD
Figure 1. Timing Diagram
VCH AVCC DVCC AIN BUF T/H CURRENT MIRROR 450
⍀
VCL BUF VREF VCH AVCC 450
⍀
DVCC AIN BUF T/H VREF D0–D11 VCL
Figure 2. Analog Input Stage
AVCC CURRENT MIRROR AVCC AVCC R1 R1
Figure 5. Digital Output Stage
17k
⍀
17k
⍀
ENCODE ENCODE TIMING R2 CIRCUITS R2 AV 8k
⍀
8k
⍀
CC AVCC 2.4V V
Figure 3. ENCODE Inputs
REF 0.5mA AVCC
Figure 6. 2.4 V Reference
VREF AVCC AVCC CURRENT MIRROR C1
Figure 4. Compensation Pin, C1 REV. A –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History
Figure 1. Timing Diagram
VCH AVCC DVCC AIN BUF T/H CURRENT MIRROR 450
⍀
VCL BUF VREF VCH AVCC 450
⍀
DVCC AIN BUF T/H VREF D0–D11 VCL
Figure 2. Analog Input Stage
AVCC CURRENT MIRROR AVCC AVCC R1 R1
Figure 5. Digital Output Stage
17k
⍀
17k
⍀
ENCODE ENCODE TIMING R2 CIRCUITS R2 AV 8k
⍀
8k
⍀
CC AVCC 2.4V V
Figure 3. ENCODE Inputs
REF 0.5mA AVCC
Figure 6. 2.4 V Reference
VREF AVCC AVCC CURRENT MIRROR C1
Figure 4. Compensation Pin, C1 REV. A –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History
