Datasheet PIC32MZ Graphics (DA) Family (Microchip)

ManufacturerMicrochip
Description32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash, 640 KB SRAM, and 32 MB DDR2 SDRAM) with XLP Technology
Pages / Page808 / 1 — PIC32MZ Graphics (DA) Family. 32-bit Graphics Applications MCUs (up to 2 …
Revision05-30-2017
File Format / SizePDF / 15.6 Mb
Document Languageenglish

PIC32MZ Graphics (DA) Family. 32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash,

Datasheet PIC32MZ Graphics (DA) Family Microchip, Revision: 05-30-2017

Model Line for this Datasheet

PIC32MZ1025DAA169
PIC32MZ1025DAA176
PIC32MZ1025DAA288
PIC32MZ1025DAB169
PIC32MZ1025DAB176
PIC32MZ1025DAB288
PIC32MZ1025DAG169
PIC32MZ1025DAG176
PIC32MZ1025DAH169
PIC32MZ1025DAH176
PIC32MZ1064DAA169
PIC32MZ1064DAA176
PIC32MZ1064DAA288
PIC32MZ1064DAB169
PIC32MZ1064DAB176
PIC32MZ1064DAB288
PIC32MZ1064DAG169
PIC32MZ1064DAG176
PIC32MZ1064DAH169
PIC32MZ1064DAH176
PIC32MZ2025DAA169
PIC32MZ2025DAA176
PIC32MZ2025DAA288
PIC32MZ2025DAB169
PIC32MZ2025DAB176
PIC32MZ2025DAB288
PIC32MZ2025DAG169
PIC32MZ2025DAG176
PIC32MZ2025DAH169
PIC32MZ2025DAH176
PIC32MZ2064DAA169
PIC32MZ2064DAA176
PIC32MZ2064DAA288
PIC32MZ2064DAB169
PIC32MZ2064DAB176
PIC32MZ2064DAB288
PIC32MZ2064DAG169
PIC32MZ2064DAG176
PIC32MZ2064DAH169
PIC32MZ2064DAH176

Text Version of Document

PIC32MZ Graphics (DA) Family 32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash, 640 KB SRAM, and 32 MB DDR2 SDRAM) with XLP Technology Operating Conditions Advanced Analog Features
• 2.2V to 3.6V, -40ºC to +85ºC, DC to 200 MHz • 12-bit ADC modules: • 2.2V to 3.6V, -40ºC to +105ºC (Planned) - 18 Msps with up to six ADC circuits (five dedicated and one shared)
Core: 200 MHz / 330 DMIPS MIPS32® microAptiv™
- Up to 45 analog input • 32 KB I-Cache, 32 KB D-Cache - Can operate during Sleep and Idle modes • MMU for optimum embedded OS execution - Multiple trigger sources • microMIPS™ mode for up to 35% smaller code size - Six Digital Comparators and six Digital Filters • DSP-enhanced core: - Four 64-bit accumulators • Two Comparators with 32 programmable voltage references - Single-cycle MAC, saturating and fractional math • Temperature sensor with ±2ºC accuracy • Code-efficient (C and Assembly) architecture • Charge Time Measurement Unit (CTMU)
Clock Management Communication Interfaces
• Programmable PLLs and oscillator clock sources • Two CAN modules (with dedicated DMA channels): • Dedicated PLL for DDR2 - 2.0B Active with DeviceNet™ addressing support • Fail-Safe Clock Monitor • Six UART modules (25 Mbps): • Independent Watchdog and Deadman Timers - Supports LIN 1.2 and IrDA® protocols • Fast wake-up and start-up • Six 4-wire SPI modules (up to 50 MHz)
Power Management
• SQI configurable as additional SPI module (up to 80 MHz) • Various power management options for extreme power • Fiv e I2C modules (up to 1 Mbaud) with SMBus support reduction (VBAT, Deep Sleep, Sleep and Idle) • Parallel Master Port (PMP) • Deep Sleep current: < 1 µA (typical) • Peripheral Pin Select (PPS) to enable function remap • Integrated POR and BOR • Programmable High/Low-Voltage Detect (HLVD) on V
Timers/Output Compare/Input Capture
DDIO and High-Voltage Detect (HVD) on VDDR1V8 • Nine 16-bit and up to four 32-bit timers/counters
Memory Interfaces
• Nine Output Compare (OC) modules • Nine Input Capture (IC) modules • DDR2 SDRAM interface (up to DDR2-400) • Real-Time Clock and Calendar (RTCC) module • SD/SDIO/eMMC bus interface (up to 50 MHz) • Serial Quad Interface (up to 80 MHz)
Input/Output
• External Bus Interface (up to 50 MHz) • 5V-tolerant pins with up to 32 mA source/sink
Graphics Features
• Selectable open drain, pull-ups, and pull-downs • 3-layer Graphics Controller with up to 24-bit color support • Selectable slew rate control • High-performance 2D Graphics Processing Unit (GPU) • External interrupts on all I/O pins
Audio Interfaces
• PPS to enable function remap • Audio data communication: I2S, LJ, and RJ
Qualification and Class B Support
• Audio control interfaces: SPI and I2C • AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) (Planned) • Audio master clock: Fractional clock frequencies with USB • Class B Safety Library, IEC 60730 synchronization • Back-up internal oscillator
High-Speed Communication Interfaces (with Debugger Development Support Dedicated DMA)
• In-circuit and in-application programming • USB 2.0-compliant High-Speed On-The-Go (OTG) controller • 4-wir e MIPS® Enhanced JTAG interface • 10/100 Mbps Ethernet MAC with MII and RMII interface • Unlimited software and 12 complex breakpoints
Security Features
• IEEE 1149.2-compatible (JTAG) boundary scan • Crypto Engine with a RNG for data encryption/decryption and • Non-intrusive hardware-based instruction trace authentication (AES, 3DES, SHA, MD5, and HMAC) • Advanced memory protection:
Integrated Software Libraries and Tools
- Peripheral and memory region access control • C/C++ compiler with native DSP/fractional support • MPLAB® Harmony Integrated Software Framework
Direct Memory Access (DMA)
• TCP/IP, USB, Graphics, and mTouch™ middleware • Eight channels with automatic data size detection • MFi, Android™, and Bluetooth® audio frameworks • Programmable Cyclic Redundancy Check (CRC) • RTOS Kernels: Express Logic ThreadX, FreeRTOS™, OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS®
Packages Type LFBGA LQFP Pin Count
169 288 176
I/O Pins (up to)
120 120 120
Contact/Lead Pitch
0.8 mm 0.8 mm 0.4 mm
Dimensions
11x11 mm 15x15 mm 20x20 mm  2015-2017 Microchip Technology Inc. DS60001361E-page 1 Document Outline TABLE 1: PIC32MZ DA Features Common to All Devices TABLE 2: 169-pin LFBGA PIC32MZ DA Features TABLE 3: 176-pin LQFP PIC32MZ DA Features TABLE 4: 288-pin LFBGA PIC32MZ DA Features TABLE 5: Pin Names for 169-pin Devices (Continued) TABLE 6: Pin Names for 176-pin Devices (Continued) TABLE 7: Pin Names for 288-pin Devices (Continued) 1.0 Device Overview FIGURE 1-1: PIC32MZ DA Family Block Diagram TABLE 1-1: ADC Pinout I/O Descriptions Table 1-2: Oscillator Pinout I/O Descriptions Table 1-3: IC1 through IC9 Pinout I/O Descriptions Table 1-4: OC1 Through OC9 Pinout I/O Descriptions Table 1-5: External Interrupts Pinout I/O Descriptions Table 1-6: PORTA through PORTK Pinout I/O Descriptions (Continued) Table 1-7: Timer1 through Timer9 and rTCC Pinout I/O Descriptions Table 1-8: UART1 through UART6 Pinout I/O Descriptions Table 1-9: SPI1 through SPI 6 Pinout I/O Descriptions Table 1-10: I2C1 through I2C5 Pinout I/O Descriptions Table 1-11: Comparator 1, Comparator 2 and CVref Pinout I/O Descriptions Table 1-12: PMP Pinout I/O Descriptions Table 1-13: EBI Pinout I/O Descriptions (Continued) Table 1-14: USB Pinout I/O Descriptions Table 1-15: CAN1 and CAN2 Pinout I/O Descriptions Table 1-16: Ethernet MII I/O Descriptions Table 1-17: Ethernet RMII Pinout I/O Descriptions Table 1-18: SQI1 Pinout I/O Descriptions TABLE 1-19: SDHC Pinout I/O Descriptions TABLE 1-20: CTMU Pinout I/O Descriptions Table 1-21: Graphics LCD (GLCD) Controller Pinout I/O Descriptions TABLE 1-22: DDR2 SDRAM Controller Pinout I/O Descriptions (Continued) TABLE 1-23: Power, Ground, and Voltage Reference Pinout I/O Descriptions (Continued) Table 1-24: JTAG, Trace, and Programming/Debugging Pinout I/O Descriptions 2.0 Guidelines for Getting Started with 32-bit Microcontrollers 2.1 Basic Connection Requirements 2.2 Decoupling Capacitors FIGURE 2-1: Recommended Minimum Connection 2.3 Master Clear (MCLR) Pin FIGURE 2-2: Example of MCLR Pin Connections 2.4 ICSP Pins 2.5 JTAG 2.6 Trace 2.7 External Oscillator Pins FIGURE 2-3: Suggested Oscillator Circuit Placement 2.8 Unused I/Os 2.9 Designing for High-Speed Peripherals TABLE 2-1: Peripherals That produce HS Signals on External Pins FIGURE 2-4: Series Resistor FIGURE 2-5: EMI/EMC/EFT Suppression Circuit 2.10 Typical Application Connection Example FIGURE 2-6: Graphics Application 3.0 CPU 3.1 Features FIGURE 3-1: PIC32MZ DA Family Microprocessor Core Block Diagram 3.2 Architecture Overview Table 3-1: MIPS32 microAptiv Microprocessor Core High-Performance Integer Multiply/Divide Unit Latencies and Repeat Rates Table 3-2: DSP-related Latencies and Repeat Rates Table 3-3: Coprocessor 0 Registers (Continued) 3.3 Power Management 3.4 L1 Instruction and Data Caches 3.5 EJTAG Debug Support 3.6 MIPS® DSP ASE Extension 3.7 microAptiv Core Configuration Register 3-1: Config: Configuration Register; CP0 Register 16, Select 0 Register 3-2: Config1: Configuration Register 1; CP0 Register 16, Select 1 Register 3-3: Config3: Configuration Register 3; CP0 Register 16, Select 3 Register 3-4: Config5: Configuration Register 5; CP0 Register 16, Select 5 Register 3-5: Config7: Configuration Register 7; CP0 Register 16, Select 7 4.0 Memory Organization 4.1 Memory Layout FIGURE 4-1: PIC32MZ DA Family Memory Map Table 4-1: Address Mapping Table FIGURE 4-2: Boot and Alias Memory Map Table 4-2: SFR Memory Map TABLE 4-3: Boot Flash 1 Sequence and Configuration Words Summary TABLE 4-4: Boot Flash 2 Sequence and Configuration Words Summary Register 4-1: BFxSEQ3/ABFxSEQ3: Boot Flash ‘x’ Sequence Word 0 Register (‘x’ = 1 and 2) 4.2 DDR2 SDRAM FIGURE 4-3: DDR2 SDRAM Block Diagram 4.3 Timing Parameters Table 4-5: Timing Parameters 4.4 System Bus Arbitration TABLE 4-6: Initiators to Targets Access Association (Continued) Table 4-7: Initiator ID and Arbitration 4.5 Permission Access and System Bus Registers Table 4-8: System Bus Targets and Associated Protection Registers (Continued) TABLE 4-9: System Bus Violation Flag Register Map TABLE 4-10: System Bus Target Protection Group 0 (T0PGV0 - T0PGV3) Register Map TABLE 4-11: System Bus Target Protection Group 1 Register Map (Continued) TABLE 4-12: System Bus Target Protection Group 2 Register Map TABLE 4-13: System Bus Target Protection Group 3 Register Map TABLE 4-14: System Bus Target Protection Group 4 Register Map (Continued) TABLE 4-15: System Bus Target Protection Group 5 Register Map (Continued) TABLE 4-16: System Bus Target Protection Group 6 Register Map TABLE 4-17: System Bus Target Protection Group 7 Register Map TABLE 4-18: System Bus Target Protection Group 8 Register Map TABLE 4-19: System Bus Target Protection Group 9 Register Map TABLE 4-20: System Bus Target Protection Group 10 Register Map TABLE 4-21: System Bus Target Protection Group 11 Register Map TABLE 4-22: System Bus Target Protection Group 12 Register Map TABLE 4-23: System Bus Target Protection Group 13 Register Map TABLE 4-24: System Bus Target Protection Group 14 Register Map TABLE 4-25: System Bus Target Protection Group 15 Register Map TABLE 4-26: System Bus Target Protection Group 16 Register Map (Continued) Register 4-2: SBFlag0: System Bus Status Flag Register 0 Register 4-3: SBFlag1: System Bus Status Flag Register 1 Register 4-4: SBFlag2: System Bus Status Flag Register 2 Register 4-5: SBFlag3: System Bus Status Flag Register 3 Register 4-6: SBTxELOG1: System Bus Target ‘x’ Error Log Register 1 (‘x’ = 0-13) (Continued) Register 4-7: SBTxELOG2: System Bus Target ‘x’ Error Log Register 2 (‘x’ = 0-13) Register 4-8: SBTxECON: System Bus Target ‘x’ Error Control Register (‘x’ = 0-13) Register 4-9: SBTxECLRS: System Bus Target ‘x’ Single Error Clear Register (‘x’ = 0-13) Register 4-10: SBTxECLRM: System Bus Target ‘x’ Multiple Error Clear Register (‘x’ = 0-13) Register 4-11: SBTxREGy: System Bus Target ‘x’ Region ‘y’ Register (‘x’ = 0-13; ‘y’ = 0-8) Register 4-12: SBTxRDy: System Bus Target ‘x’ Region ‘y’ Read Permissions Register (‘x’ = 0-13; ‘y’ = 0-8) Register 4-13: SBTxWRy: System Bus Target ‘x’ Region ‘y’ Write Permissions Register (‘x’ = 0-13; ‘y’ = 0-8) 5.0 Flash Program Memory 5.1 Flash Control Registers TABLE 5-1: Flash Controller Register Map Register 5-1: NVMCON: Programming Control Register Register 5-2: NVMKEY: Programming Unlock Register Register 5-3: NVMADDR: Flash Address Register Register 5-4: NVMDATAx: Flash Data Register (x = 0-3) Register 5-5: NVMSRCADDR: Source Data Address Register Register 5-6: NVMPWP: Program Flash Write-Protect Register Register 5-7: NVMBWP: Flash Boot (Page) Write-Protect Register Register 5-8: NVMCON2: Programming Control Register 2 6.0 Resets FIGURE 6-1: System Reset Block Diagram 6.1 Reset Control Registers TABLE 6-1: Resets Register Map Register 6-1: RCON: Reset Control Register Register 6-2: RSWRST: Software Reset Register Register 6-3: RNMICON: Non-Maskable Interrupt (NMI) Control Register Register 6-4: PWRCON: Power Control Register 7.0 CPU Exceptions and Interrupt Controller FIGURE 7-1: CPU Exceptions and Interrupt Controller Module Block Diagram 7.1 CPU Exceptions Table 7-1: MIPS32® microAptiv™ Microprocessor Core Exception Types 7.2 Interrupts Table 7-2: Interrupt IRQ, Vector and Bit Location 7.3 Interrupt Control Registers Table 7-3: Interrupt Register Map Register 7-1: INTCON: Interrupt Control Register Register 7-2: PRISS: Priority Shadow Select Register Register 7-3: INTSTAT: Interrupt Status Register Register 7-4: IPTMR: Interrupt Proximity Timer Register Register 7-5: IFSx: Interrupt Flag Status Register Register 7-6: IECx: Interrupt Enable Control Register Register 7-7: IPCx: Interrupt Priority Control Register Register 7-8: OFFx: Interrupt Vector Address Offset Register (x = 0-190) 8.0 Oscillator Configuration FIGURE 8-1: PIC32MZ DA Family Oscillator Diagram Table 8-1: System and Peripheral clock Distribution 8.1 Fail-Safe Clock Monitor (FSCM) 8.2 Oscillator Control Registers TABLE 8-2: Oscillator Configuration Register Map Register 8-1: OSCCON: Oscillator Control Register Register 8-2: OSCTUN: FRC Tuning Register Register 8-3: SPLLCON: System PLL Control Register Register 8-4: REFOxCON: Reference Oscillator Control Register (‘x’ = 1-4) Register 8-5: REFOxTRIM: Reference Oscillator Trim Register (‘x’ = 1-4) Register 8-6: PBxDIV: Peripheral Bus ‘x’ Clock Divisor Control Register (‘x’ = 1-7) Register 8-7: SLEWCON: Oscillator Slew Control Register Register 8-8: CLKSTAT: Oscillator Clock Status Register 9.0 Prefetch Module 9.1 Features FIGURE 9-1: Prefetch Module Block Diagram 9.2 Prefetch Control Registers TABLE 9-1: Prefetch Register Map Register 9-1: PRECON: Prefetch Module Control Register 10.0 Direct Memory Access (DMA) Controller FIGURE 10-1: DMA Block Diagram 10.1 DMA Control Registers TABLE 10-1: DMA Global Register Map TABLE 10-2: DMA CRC Register Map TABLE 10-3: DMA Channel 0 THROUGH Channel 7 Register Map Register 10-1: DMACON: DMA Controller Control Register Register 10-2: DMASTAT: DMA Status Register Register 10-3: DMAADDR: DMA Address Register Register 10-4: DCRCCON: DMA CRC Control Register Register 10-5: DCRCDATA: DMA CRC Data Register Register 10-6: DCRCXOR: DMA CRCXOR Enable Register Register 10-7: DCHxCON: DMA Channel x Control Register Register 10-8: DCHxECON: DMA Channel x Event Control Register Register 10-9: DCHxINT: DMA Channel x Interrupt Control Register Register 10-10: DCHxSSA: DMA Channel x Source Start Address Register Register 10-11: DCHxDSA: DMA Channel x Destination Start Address Register Register 10-12: DCHxSSIZ: DMA Channel x Source Size Register Register 10-13: DCHxDSIZ: DMA Channel x Destination Size Register Register 10-14: DCHxSPTR: DMA Channel x Source Pointer Register Register 10-15: DCHxDPTR: DMA Channel x Destination Pointer Register Register 10-16: DCHxCSIZ: DMA Channel x Cell-Size Register Register 10-17: DCHxCPTR: DMA Channel x Cell Pointer Register Register 10-18: DCHxDAT: DMA Channel x Pattern Data Register 11.0 Hi-Speed USB with On- The-Go (OTG) FIGURE 11-1: PIC32MZ DA Family USB Interface Diagram 11.1 USB OTG Control Registers TABLE 11-1: USB Register Map 1 TABLE 11-2: USB Register Map 2 Register 11-1: USBCSR0: USB Control Status Register 0 Register 11-2: USBCSR1: USB Control Status Register 1 Register 11-3: USBCSR2: USB Control Status Register 2 Register 11-4: USBCSR3: USB Control Status Register 3 Register 11-5: USBIE0CSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 0) Register 11-6: USBIE0CSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 0) Register 11-7: USBIE0CSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 0) Register 11-8: USBIENCSR0: USB Indexed Endpoint Control Status Register 0 (Endpoint 1-7) Register 11-9: USBIENCSR1: USB Indexed Endpoint Control Status Register 1 (Endpoint 1-7) Register 11-10: USBIENCSR2: USB Indexed Endpoint Control Status Register 2 (Endpoint 1-7) Register 11-11: USBIENCSR3: USB Indexed Endpoint Control Status Register 3 (Endpoint 1-7) Register 11-12: USBFIFOx: USB FIFO Data Register ‘x’ (‘x’ = 0-7) Register 11-13: USBOTG: USB OTG Control/Status Register Register 11-14: USBFIFOA: USB FIFO Address Register Register 11-15: USBHWVER: USB Hardware Version Register Register 11-16: USBINFO: USB Information Register Register 11-17: USBEOFRST: USB End-of-Frame/Soft Reset Control Register Register 11-18: USBEXTXA: USB Endpoint ‘x’ Transmit Address Register Register 11-19: USBExRXA: USB Endpoint ‘x’ Receive Address Register Register 11-20: USBDMAINT: USB DMA Interrupt Register Register 11-21: USBDMAxC: USB DMA Channel ‘x’ Control Register (‘x’ = 1-8) Register 11-22: USBDMAxA: USB DMA Channel ‘x’ Memory Address Register (‘x’ = 1-8) Register 11-23: USBDMAxN: USB DMA Channel ‘x’ Count Register (‘x’ = 1-8) Register 11-24: USBEXRPC: USB Endpoint ‘x’ Request Packet Count Register (Host Mode Only) (‘x’ = 1-7) Register 11-25: USBDPBFD: USB Double Packet Buffer Disable Register Register 11-26: USBTMCON1: USB Timing Control Register 1 Register 11-27: USBTMCON2: USB Timing Control Register 2 Register 11-28: USBLPMR1: USB Link Power Management Control Register 1 Register 11-29: USBLPMR2: USB Link Power Management Control Register 2 Register 11-30: USBCRCON: USB Clock/Reset Control Register 12.0 I/O Ports FIGURE 12-1: Block Diagram of a Typical Multiplexed Port Structure 12.1 Parallel I/O (PIO) Ports 12.2 CLR, SET, and INV Registers 12.3 Slew Rate Registers 12.4 Peripheral Pin Select (PPS) FIGURE 12-2: Remappable Input Example for U1RX TABLE 12-1: Input Pin Selection FIGURE 12-3: Example of Multiplexing of Remappable Output for RPF0 Table 12-2: Output Pin Selection 12.5 I/O Ports Control Registers TABLE 12-3: PORTA Register Map TABLE 12-4: PORTB Register Map TABLE 12-5: PORTC Register Map TABLE 12-6: PORTD Register Map TABLE 12-7: PORTE Register Map TABLE 12-8: PORTF Register Map TABLE 12-9: PORTG Register Map TABLE 12-10: PORTH Register Map TABLE 12-11: PORTJ Register Map TABLE 12-12: PORTK Register Map Table 12-13: Peripheral Pin Select Input Register Map Table 12-14: Peripheral Pin Select Output Register Map Register 12-1: [pin name]R: Peripheral Pin Select Input Register Register 12-2: RPnR: Peripheral Pin Select Output Register Register 12-3: CNCONx: Change Notice control for PORTx Register (‘x’ = A – G) 13.0 Timer1 13.1 Additional Supported Features FIGURE 13-1: Timer1 Block Diagram 13.2 Timer1 Control Register TABLE 13-1: Timer1 Register Map Register 13-1: T1CON: Type A Timer Control Register 14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9 14.1 Additional Features FIGURE 14-1: Timer2 through Timer9 Block Diagram (16-bit) FIGURE 14-2: Timer2/3, Timer4/5, Timer6/7, and Timer8/9 Block Diagram (32-bit) 14.2 Timer2-Timer9 Control Registers TABLE 14-1: Timer2 THROUGH Timer9 Register Map Register 14-1: TxCON: Type B Timer Control Register (‘x’ = 2-9) 15.0 Input Capture FIGURE 15-1: Input Capture Block Diagram Table 15-1: Timer Source Configurations 15.1 Input Capture Control Registers TABLE 15-2: Input Capture 1 THROUGH Input Capture 9 Register Map Register 15-1: ICxCON: Input Capture x Control Register 16.0 Output Compare FIGURE 16-1: Output Compare Module Block Diagram Table 16-1: Timer Source Configurations 16.1 Output Compare Control Registers TABLE 16-2: Output Compare 1 THROUGH Output Compare 9 Register Map Register 16-1: OCxCON: Output Compare ‘x’ Control Register 17.0 Deadman Timer (DMT) FIGURE 17-1: Deadman Timer Block diagram 17.1 Deadman Timer Control Registers TABLE 17-1: Deadman Timer Register Map Register 17-1: DMTCON: Deadman Timer Control Register Register 17-2: DMTPRECLR: Deadman Timer Preclear Register Register 17-3: DMTCLR: Deadman Timer Clear Register Register 17-4: DMTSTAT: Deadman Timer Status Register Register 17-5: DMTCNT: Deadman Timer Count Register Register 17-6: DMTPSCNT: Post Status Configure DMT Count Status Register Register 17-7: DMTPSINTV: Post Status Configure DMT Interval Status Register 18.0 Watchdog Timer (WDT) Figure 18-1: Watchdog Timer Block Diagram 18.1 Watchdog Timer Control Registers TABLE 18-1: Watchdog Timer Register Map Register 18-1: WDTCON: Watchdog Timer Control Register 19.0 Deep Sleep Watchdog Timer (DSWDT) Figure 19-1: Deep Sleep Watchdog Timer Block Diagram 20.0 Real-Time Clock and Calendar (RTCC) FIGURE 20-1: RTCC Block Diagram 20.1 RTCC Control Registers TABLE 20-1: RTCC Register Map Register 20-1: RTCCON: Real-Time Clock and Calendar Control Register Register 20-2: RTCALRM: Real-Time Clock ALARM Control Register Register 20-3: RTCTIME: Real-Time Clock Time Value Register Register 20-4: RTCDATE: Real-Time Clock Date Value Register Register 20-5: ALRMTIME: Alarm Time Value Register Register 20-6: ALRMDATE: Alarm Date Value Register 21.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S) FIGURE 21-1: SPI/I2S Module Block Diagram 21.1 SPI Control Registers Table 21-1: SPI1 Through SPI6 Register Map Register 21-1: SPIx CON: SPI Control Register Register 21-2: SPIxCON2: SPI Control Register 2 Register 21-3: SPIxSTAT: SPI Status Register 22.0 Serial Quad Interface (SQI) FIGURE 22-1: SQI Module Block Diagram 22.1 SQI Control Registers Table 22-1: Serial Quadrature Interface (SQI) Register Map Register 22-1: SQI1XCON1: SQI XIP Control Register 1 Register 22-2: SQI1XCON2: SQI XIP Control Register 2 Register 22-3: SQI1CFG: SQI Configuration Register Register 22-4: SQI1CON: SQI Control Register Register 22-5: SQI1CLKCON: SQI Clock Control Register Register 22-6: SQI1CMDTHR: SQI Command Threshold Register Register 22-7: SQI1INTTHR: SQI Interrupt Threshold Register Register 22-8: SQI1INTEN: SQI Interrupt Enable Register Register 22-9: SQI1INTSTAT: SQI Interrupt Status Register Register 22-10: SQI1TXDATA: SQI Transmit Data Buffer Register Register 22-11: SQI1RXDATA: SQI Receive Data Buffer Register Register 22-12: SQI1STAT1: SQI Status Register 1 Register 22-13: SQI1STAT2: SQI Status Register 2 Register 22-14: SQI1BDCON: SQI Buffer Descriptor Control Register Register 22-15: SQI1BDCURADD: SQI Buffer Descriptor Current Address Register Register 22-16: SQI1BDBASEADD: SQI Buffer Descriptor Base Address Register Register 22-17: SQI1BDSTAT: SQI Buffer Descriptor Status Register Register 22-18: SQI1BDPOLLCON: SQI Buffer Descriptor Poll Control Register Register 22-19: SQI1BDTXDSTAT: SQI Buffer Descriptor DMA Transmit Status Register Register 22-20: SQI1BDRXDSTAT: SQI Buffer Descriptor DMA Receive Status Register Register 22-21: SQI1THR: SQI Threshold Control Register Register 22-22: SQI1INTSIGEN: SQI Interrupt Signal Enable Register Register 22-23: SQI1TAPCON: SQI TAP Control Register Register 22-24: SQI1MEMSTAT: SQI Memory Status Control Register Register 22-25: SQI1XCON3: SQI XIP Control Register 3 Register 22-26: SQI1XCON4: SQI XIP Control Register 4 23.0 Inter-Integrated Circuit (I2C) FIGURE 23-1: I2C Block Diagram 23.1 I2C Control Registers TABLE 23-1: I2C1 Through I2C5 Register Map Register 23-1: I2CxCON: I2C Control Register Register 23-2: I2CxSTAT: I2C Status Register 24.0 Universal Asynchronous Receiver Transmitter (UART) FIGURE 24-1: UART Simplified Block Diagram 24.1 UART Control Registers TABLE 24-1: UART1 THROUGH UART6 Register Map Register 24-1: UxMODE: UARTx Mode Register Register 24-2: UxSTA: UARTx Status and Control Register FIGURE 24-2: UART Reception FIGURE 24-3: Transmission (8-bit or 9-bit Data) 25.0 Parallel Master Port (PMP) FIGURE 25-1: PMP Module Pinout and Connections to External Devices 25.1 Control Registers TABLE 25-1: Parallel Master Port Register Map Register 25-1: PMCON: Parallel Port Control Register Register 25-2: PMMODE: Parallel Port Mode Register Register 25-3: PMADDR: Parallel Port Address Register Register 25-4: PMDOUT: Parallel Port Output Data Register Register 25-5: PMDIN: Parallel Port Input Data Register Register 25-6: PMAEN: Parallel Port Pin Enable Register Register 25-7: PMSTAT: Parallel Port Status Register (Slave modes only) Register 25-8: PMWADDR: Parallel Port Write Address Register Register 25-9: PMRADDR: Parallel Port Read Address Register Register 25-10: PMRDIN: Parallel Port Read Input Data Register 26.0 External Bus Interface (EBI) FIGURE 26-1: EBI System Block Diagram 26.1 EBI Control Registers TABLE 26-1: EBI Register Map Register 26-1: EBICSX: External Bus Interface Chip Select Register (‘x’ = 0-3) Register 26-2: EBIMSKx: External Bus Interface Address Mask Register (‘x’ = 0-3) Register 26-3: EBISMTx: External Bus Interface Static Memory Timing Register (‘x’ = 0-2) Register 26-4: EBIFTRPD: External Bus Interface Flash Timing Register Register 26-5: EBISMCON: External Bus Interface Static Memory Control Register 27.0 Crypto Engine Table 27-1: Crypto Engine Performance FIGURE 27-1: Crypto Engine Block Diagram 27.1 Crypto Engine Control Registers Table 27-2: Crypto Engine Register Map Register 27-1: CEVER: Crypto Engine Revision, Version, and ID Register Register 27-2: CECON: Crypto Engine Control Register Register 27-3: CEBDADDR: Crypto Engine Buffer Descriptor Register Register 27-4: CEBDPADDR: Crypto Engine Buffer Descriptor Processor Register Register 27-5: CESTAT: Crypto Engine Status Register Register 27-6: CEINTSRC: Crypto Engine Interrupt Source Register Register 27-7: CEINTEN: Crypto Engine Interrupt Enable Register Register 27-8: CEPOLLCON: Crypto Engine Poll Control Register Register 27-9: CEHDLEN: Crypto Engine Header Length Register Register 27-10: CETRLLEN: Crypto Engine Trailer Length Register 27.2 Crypto Engine Buffer Descriptors Table 27-3: Crypto Engine Buffer Descriptors FIGURE 27-2: Format of BD_CTRL FIGURE 27-3: Format of BD_SADDR FIGURE 27-4: Format of BD_SADDR FIGURE 27-5: Format of BD_SRCADDR FIGURE 27-6: Format of BD_DSTADDR FIGURE 27-7: Format of BD_NXTADDR FIGURE 27-8: Format of BD_UPDPTR FIGURE 27-9: Format of BD_MSG_LEN FIGURE 27-10: Format of BD_ENC_OFF 27.3 Security Association Structure FIGURE 27-11: Crypto Engine Security Association Structure FIGURE 27-12: Format of SA_CTRL 28.0 Random Number Generator (RNG) FIGURE 28-1: Random Number Generator Block Diagram 28.1 RNG Control Registers Table 28-1: Random Number Generator (RNG) Register Map Register 28-1: RNGVER: Random Number Generator Version Register Register 28-2: RNGCON: Random Number Generator Control Register Register 28-3: RNGPOLYx: Random Number Generator Polynomial Register ‘x’ (‘x’ = 1 or 2) Register 28-4: RNGNUMGENx: Random Number Generator Register ‘x’ (‘x’ = 1 or 2) Register 28-5: RNGSEEDx: True Random Number Generator Seed Register ‘x’ (‘x’ = 1 or 2) Register 28-6: RNGCNT: True Random Number Generator Count Register 29.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to- Digital Converter (ADC) EQUATION 29-1: ADC Throughput Rate FIGURE 29-1: ADC Block Diagram FIGURE 29-2: S&H Block Diagram FIGURE 29-3: FIFO Block Diagram 29.1 ADC Control Registers Table 29-1: ADC Register Map Register 29-1: ADCCON1: ADC Control Register 1 Register 29-2: ADCCON2: ADC Control Register 2 Register 29-3: ADCCON3: ADC Control Register 3 Register 29-4: ADCTRGMODE: ADC Triggering Mode for Dedicated ADC Register Register 29-5: ADCIMCON1: ADC Input Mode Control Register 1 Register 29-6: ADCIMCON2: ADC Input Mode Control Register 2 Register 29-7: ADCIMCON3: ADC Input Mode Control Register 3 Register 29-8: ADCGIRQEN1: ADC Global Interrupt Enable Register 1 Register 29-9: ADCGIRQEN2: ADC Global Interrupt Enable Register 2 Register 29-10: ADCCSS1: ADC Common Scan Select Register 1 Register 29-11: ADCCSS2: ADC Common Scan Select Register 2 Register 29-12: ADCDSTAT1: ADC Data Ready Status Register 1 Register 29-13: ADCDSTAT2: ADC Data Ready Status Register 2 Register 29-14: ADCCMPENx: ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 6) Register 29-15: ADCCMPx: ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 6) Register 29-16: ADCFLTRx: ADC Digital Filter ‘x’ Register (‘x’ = 1 through 6) Register 29-17: ADCTRG1: ADC Trigger Source 1 Register Register 29-18: ADCTRG2: ADC Trigger Source 2 Register Register 29-19: ADCTRG3: ADC Trigger Source 3 Register Register 29-20: ADCCMPCON1: ADC Digital Comparator 1 Control Register Register 29-21: ADCCMPCONx: ADC Digital Comparator ‘x’ Control Register (‘x’ = 2 through 6) Register 29-22: ADCFSTAT: ADC FIFO Status Register Register 29-23: ADCFIFO: ADC FIFO Data Register Register 29-24: ADCBASE: ADC Base Register Register 29-25: ADCDATAx: ADC Output Data Register ‘x’ (‘x’ = 0 through 43) Register 29-26: ADCTRGSNS: ADC Trigger Level/Edge Sensitivity Register Register 29-27: ADCxTIME: Dedicated ADCx Timing Register (‘x’ = 0 through 4) Register 29-28: ADCEIEN1: ADC Early Interrupt Enable Register 1 Register 29-29: ADCEIEN2: ADC Early Interrupt Enable Register 2 Register 29-30: ADCEISTAT1: ADC Early Interrupt Status Register 1 Register 29-31: ADCEISTAT2: ADC Early Interrupt Status Register 2 Register 29-32: ADCANCON: ADC Analog Warm-up Control Register Register 29-33: ADCxCFG: ADCx Configuration Register (‘x’ = 1 through 4 and 7) Register 29-34: ADCSYSCFG1: ADC System Configuration Register 1 Register 29-35: ADCSYSCFG2: ADC System Configuration Register 2 30.0 Controller Area Network (CAN) FIGURE 30-1: PIC32 CAN Module Block Diagram 30.1 CAN Control Registers TABLE 30-1: CAN1 Register Summary for PIC32MZXXXXECF and PIC32MZXXXXECH Devices TABLE 30-2: CAN2 Register Summary for PIC32MZXXXXECF and PIC32MZXXXXECH Devices Register 30-1: CiCON: CAN Module Control Register Register 30-2: CiCFG: CAN Baud Rate Configuration Register Register 30-3: CiINT: CAN Interrupt Register Register 30-4: CiVEC: CAN Interrupt Code Register Register 30-5: CiTREC: CAN Transmit/Receive Error Count Register Register 30-6: CiFSTAT: CAN FIFO Status Register Register 30-7: CiRXOVF: CAN Receive FIFO Overflow Status Register Register 30-8: CiTMR: CAN TImer Register Register 30-9: CiRXMn: CAN Acceptance Filter Mask n Register (n = 0, 1, 2 or 3) Register 30-10: CiFLTCON0: CAN Filter Control Register 0 Register 30-11: CiFLTCON1: CAN Filter Control Register 1 Register 30-12: CiFLTCON2: CAN Filter Control Register 2 Register 30-13: CiFLTCON3: CAN Filter Control Register 3 Register 30-14: CiFLTCON4: CAN Filter Control Register 4 Register 30-15: CiFLTCON5: CAN Filter Control Register 5 Register 30-16: CiFLTCON6: CAN Filter Control Register 6 Register 30-17: CiFLTCON7: CAN Filter Control Register 7 Register 30-18: CiRXFn: CAN Acceptance Filter n Register 7 (n = 0 through 31) Register 30-19: CiFIFOBA: CAN Message Buffer Base Address Register Register 30-20: CiFIFOCONn: CAN FIFO Control Register (n = 0 through 31) Register 30-21: CiFIFOINTn: CAN FIFO Interrupt Register (n = 0 through 31) Register 30-22: CiFIFOUAn: CAN FIFO User Address Register (n = 0 through 31) Register 30-23: CiFIFOCIn: CAN Module Message Index Register (n = 0 through 31) 31.0 Ethernet Controller FIGURE 31-1: Ethernet Controller Block Diagram TABLE 31-1: MII Mode Default Interface Signals (FMIIEN = 1, FETHIO = 1) TABLE 31-2: RMII Mode Default Interface Signals (FMIIEN = 0, FETHIO = 1) 31.1 Ethernet Control Registers TABLE 31-3: Ethernet Controller Register Summary Register 31-1: ETHCON1: Ethernet Controller Control Register 1 Register 31-2: ETHCON2: Ethernet Controller Control Register 2 Register 31-3: ETHTXST: Ethernet Controller TX Packet Descriptor Start Address Register Register 31-4: ETHRXST: Ethernet Controller RX Packet Descriptor Start Address Register Register 31-5: ETHHT0: Ethernet Controller Hash Table 0 Register Register 31-6: ETHHT1: Ethernet Controller Hash Table 1 Register Register 31-7: ETHPMM0: Ethernet Controller Pattern Match Mask 0 Register Register 31-8: ETHPMM1: Ethernet Controller Pattern Match Mask 1 Register Register 31-9: ETHPMCS: Ethernet Controller Pattern Match Checksum Register Register 31-10: ETHPMO: Ethernet Controller Pattern Match Offset Register Register 31-11: ETHRXFC: Ethernet Controller Receive Filter Configuration Register Register 31-12: ETHRXWM: Ethernet Controller Receive Watermarks Register Register 31-13: ETHIEN: Ethernet Controller Interrupt Enable Register Register 31-14: ETHIRQ: Ethernet Controller Interrupt Request Register Register 31-15: ETHSTAT: Ethernet Controller Status Register Register 31-16: ETHRXOVFLOW: Ethernet Controller Receive Overflow Statistics Register Register 31-17: ETHFRMTXOK: Ethernet Controller Frames Transmitted OK Statistics Register Register 31-18: ETHSCOLFRM: Ethernet Controller Single Collision Frames Statistics Register Register 31-19: ETHMCOLFRM: Ethernet Controller Multiple Collision Frames Statistics Register Register 31-20: ETHFRMRXOK: Ethernet Controller Frames Received OK Statistics Register Register 31-21: ETHFCSERR: Ethernet Controller Frame Check Sequence Error Statistics Register Register 31-22: ETHALGNERR: Ethernet Controller Alignment Errors Statistics Register Register 31-23: EMAC1CFG1: Ethernet Controller MAC Configuration 1 Register Register 31-24: EMAC1CFG2: Ethernet Controller MAC Configuration 2 Register TABLE 31-4: Pad Operation Register 31-25: EMAC1IPGT: Ethernet Controller MAC Back-to-Back Interpacket Gap Register Register 31-26: EMAC1IPGR: Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register Register 31-27: EMAC1CLRT: Ethernet Controller MAC Collision Window/Retry Limit Register Register 31-28: EMAC1MAXF: Ethernet Controller MAC Maximum Frame Length Register Register 31-29: EMAC1SUPP: Ethernet Controller MAC PHY Support Register Register 31-30: EMAC1TEST: Ethernet Controller MAC Test Register Register 31-31: EMAC1MCFG: Ethernet Controller MAC MII Management Configuration Register TABLE 31-5: MIIM Clock Selection Register 31-32: EMAC1MCMD: Ethernet Controller MAC MII Management Command Register Register 31-33: EMAC1MADR: Ethernet Controller MAC MII Management Address Register Register 31-34: EMAC1MWTD: Ethernet Controller MAC MII Management Write Data Register Register 31-35: EMAC1MRDD: Ethernet Controller MAC MII Management Read Data Register Register 31-36: EMAC1MIND: Ethernet Controller MAC MII Management Indicators Register Register 31-37: EMAC1SA0: Ethernet Controller MAC Station Address 0 Register Register 31-38: EMAC1SA1: Ethernet Controller MAC Station Address 1 Register Register 31-39: EMAC1SA2: Ethernet Controller MAC Station Address 2 Register 32.0 Comparator FIGURE 32-1: Comparator Block Diagram 32.1 Comparator Control Registers TABLE 32-1: Comparator Register Map Register 32-1: CMxCON: Comparator Control Register Register 32-2: CMSTAT: Comparator Status Register 33.0 Comparator Voltage Reference (CVref) FIGURE 33-1: Comparator Voltage Reference Block Diagram 33.1 Comparator Voltage Reference Control Registers TABLE 33-1: Comparator Voltage Reference Register Map Register 33-1: CVRCON: Comparator Voltage Reference Control Register 34.0 High/Low-Voltage Detect (HLVD) FIGURE 34-1: High/Low-Voltage Detect (HLVD) Module Block Diagram 34.1 Control Registers TABLE 34-1: High/Low-Voltage Detect Register Map Register 34-1: HLVDCON: High/Low-Voltage Detect Control Register 35.0 Charge Time Measurement Unit (CTMU) FIGURE 35-1: CTMU Block Diagram 35.1 CTMU Control Registers TABLE 35-1: CTMU Register Map Register 35-1: CTMUCON: CTMU Control Register 36.0 Graphics LCD (GLCD) Controller FIGURE 36-1: Graphics LCD Controller Block Diagram 36.1 Graphics LCD Controller Control Registers Table 36-1: Graphics LCD Controller Register Map Register 36-1: GLCDMODE: Graphics LCD Controller Mode Register Register 36-2: GLCDCLKCON: Graphics LCD Controller Clock Control Register Register 36-3: GLCDBGCOLOR: Graphics LCD Controller Background Color Register Register 36-4: GLCDRES: Graphics LCD Controller Resolution Register Register 36-5: GLCDFPORCH: Graphics LCD Controller Front Porch Register Register 36-6: GLCDBLANKING: Graphics LCD Controller Blanking Register Register 36-7: GLCDBPORCH: Graphics LCD Controller Back Porch Register Register 36-8: GLCDCURSOR: Graphics LCD Controller Cursor Register Register 36-9: GLCDLxMODE: Graphics LCD Controller Layer ‘x’ Mode Register (‘X’ = 0-2) Register 36-10: GLCDLXSTART: Graphics LCD Controller Layer ‘X’ Start Register (‘X’ = 0-2) Register 36-11: GLCDLXSIZE: Graphics LCD Controller Layer ‘X’ SIZE Register (‘X’ = 0-2) Register 36-12: GLCDLXBADDR: Graphics LCD Controller Layer ‘X’ Base Address Register (‘X’ = 0-2) Register 36-13: GLCDLXSTRIDE: Graphics LCD Controller Layer ‘X’ Stride Register (‘X’ = 0-2) Register 36-14: GLCDLXRES: Graphics LCD Controller Layer ‘X’ Resolution Register (‘X’ = 0-2) Register 36-15: GLCDINT: Graphics LCD Controller Interrupt Register Register 36-16: GLCDSTAT: Graphics LCD Controller Status Register Register 36-17: GLCDCLUTX: GRAPHICS LCD CONTROLLER GLOBAL COLOR LOOKUP TABLE REGISTER X (‘X’=0-255) Register 36-18: GLCDCURDATAx: Graphics LCD Controller Cursor Data ‘n’ Register (‘n’ = 0-127) Register 36-19: GLCDCURLUTx: Graphics LCD Controller Cursor LUT Register ‘x’ (‘x’ = 0-15) 37.0 2-D Graphics Processing Unit (GPU) FIGURE 37-1: 2-D Graphics Processing Unit Block Diagram 38.0 DDR2 SDRAM Controller FIGURE 38-1: DDR2 SDRAM Controller Block Diagram 38.1 Control Registers Table 38-1: DDR SDRAM Controller Register Summary Register 38-1: DDRTSEL: DDR Target Select Register Register 38-2: DDRMINLIM: DDR Minimum Burst Limit Register Register 38-3: DDRRQPER: DDR Request Period Register Register 38-4: DDRMINCMD: DDR Minimum Command Register Register 38-5: DDRMEMCON: DDR Memory Control Register Register 38-6: DDRMEMCFG0: DDR Memory Configuration Register 0 Register 38-7: DDRMEMCFG1: DDR Memory Configuration Register 1 Register 38-8: DDRMEMCFG2: DDR Memory Configuration Register 2 Register 38-9: DDRMEMCFG3: DDR Memory Configuration Register 3 Register 38-10: DDRMEMCFG4: DDR Memory Configuration Register 4 Register 38-11: DDRREFCFG: DDR Refresh Configuration Register Register 38-12: DDRPWRCFG: DDR Power Configuration Register Register 38-13: DDRDLYCFG0: DDR Delay Configuration Register 0 Register 38-14: DDRDLYCFG1: DDR Delay Configuration Register 1 Register 38-15: DDRDLYCFG2: DDR Delay Configuration Register 2 Register 38-16: DDRDLYCFG3: DDR Delay Configuration Register 3 Register 38-17: DDRODTCFG: DDR On-Die Termination Configuration Register Register 38-18: DDRXFERCFG: DDR Transfer Configuration Register Register 38-19: DDRCMDISSUE: DDR Command Issue Register Register 38-20: DDRODTENCFG: DDR On-Die Termination Enable Configuration Register Register 38-21: DDRMEMWIDTH: DDR Memory Width Register Register 38-22: DDRCMD1x: DDR Host Command 1 Register ‘x’ (‘x’ = 0 through 15) Register 38-23: DDRCMD2x: DDR Host Command 2 Register ‘x’ (‘x’ = 0 through 15) Register 38-24: DDRSCLSTART: DDL SELF CALIBRATION LOGIC START REGISTER Register 38-25: DDRSCLLAT: DDL SELF CALIBRATION LOGIC LATENCY REGISTER Register 38-26: DDRSCLCFG0: DDR SCL Configuration Register 0 Register 38-27: DDRSCLCFG1: DDR SCL Configuration Register 1 Register 38-28: DDRPHYPADCON: DDR PHY Pad Control Register Register 38-29: DDRPHYDLLR: DDR PHY DLL Recalibrate Register Register 38-30: DDRPHYCLKDLY: DDR Clock Delta Delay Register 39.0 Secure Digital Host Controller (SDHC) FIGURE 39-1: Secure Digital Host Controller (SDHC) Block Diagram 39.1 Control Registers Table 39-1: SDHC SFR Summary Register 39-1: SDHCBLKCON: SDHC Block Control Register Register 39-2: SDHCARG: SDHC Argument Register Register 39-3: SDHCMODE: SDHC Mode Register Register 39-4: SDHCRESPX: SDHC Response Register ‘X’ (‘X’ = 0-3) Table 39-2: Response Bit Definition for Each Response Type Register 39-5: SDHCDATA: SDHC Data Register Register 39-6: SDHCSTAT1: SDHC Status Register 1 Register 39-7: SDHCCON1: SDHC Control Register 1 Register 39-8: SDHCCON2: SDHC Control Register 2 Register 39-9: SDHCINTSTAT: SDHC Interrupt Status Register Register 39-10: SDHCINTEN: SDHC Interrupt Flag Enable Register Register 39-11: SDHCINTSEN: SDHC Interrupt Signal Enable Register Register 39-12: SDHCSTAT2: SDHC Status Register 2 Register 39-13: SDHCCAP: SDHC Capabilities Register Register 39-14: SDHCMAXCAP: SDHC Maximum Current Capabilities Register Register 39-15: SDHCFE: SDHC Force Event Register Register 39-16: SDHCADESTAT: SDHC ADMA Error Status Register Register 39-17: SDHCAADDR: SDHC ADMA Address Register 40.0 Power-Saving Features 40.1 Power Saving with CPU Running 40.2 Power-Saving with CPU Halted FIGURE 40-1: XLP Device Block Diagram 40.3 Deep Sleep (DSCTRL) Control Registers Table 40-1: Power-Saving Modes Register Summary Register 40-1: DSCON: Deep Sleep Control Register Register 40-2: DSWAKE: Deep Sleep Wake-up Source Register Register 40-3: DSGPRx: Deep Sleep Persistent General Purpose Register ‘x’ (x = 0 through 32) 40.4 Peripheral Module Disable TABLE 40-2: Peripheral Module Disable Register Summary Table 40-3: Peripheral Module Disable Bits and Locations 41.0 Special Features 41.1 Configuration Bits 41.2 Registers TABLE 41-1: DEVCFG: Device Configuration Word Summary TABLE 41-2: ADEVCFG: Alternate Device Configuration Word Summary TABLE 41-3: Device ID, Revision, and Configuration Summary TABLE 41-4: Device Serial Number Summary TABLE 41-5: Device ADC Calibration Summary Register 41-1: DEVSIGN0/ADEVSIGN0: Device Signature Word 0 Register Register 41-2: DEVCP0/ADEVCP0: Device Code-Protect 0 Register Register 41-3: DEVCFG0/ADEVCFG0: Device Configuration Word 0 Register 41-4: DEVCFG1/ADEVCFG1: Device Configuration Word 1 Register 41-5: DEVCFG2/ADEVCFG2: Device Configuration Word 2 Register 41-6: DEVCFG3/ADEVCFG3: Device Configuration Word 3 Register 41-7: DEVCFG4/ADEVCFG4: Device Configuration Word 4 Register 41-8: DEVADCx: Device ADC Calibration Word ‘x’ (‘x’ = 0-4, 7) Register 41-9: CFGCON: Configuration Control Register Register 41-10: CFGEBIA: External Bus Interface Address Pin Configuration Register Register 41-11: CFGEBIC: External Bus Interface Control Pin Configuration Register Register 41-12: CFGPG: Permission Group Configuration Register Register 41-13: CFGCON2: Configuration Control Register 2 Register 41-14: CFGMPLL: Memory PLL Configuration Register Register 41-15: DEVID: Device and Revision ID Register Register 41-16: DEVSNx: Device Serial Number Register ‘x’ (‘x’ = 0, 1) 41.3 High-Voltage Detect (HVD1V8) on Vddr1v8 41.4 On-Chip Voltage Regulator 41.5 On-chip Temperature Sensor 41.6 Programming and Diagnostics Figure 41-1: Block Diagram of Programming, Debugging and Trace Ports 42.0 Instruction Set 43.0 Development Support 43.1 MPLAB X Integrated Development Environment Software 43.2 MPLAB XC Compilers 43.3 MPASM Assembler 43.4 MPLINK Object Linker/ MPLIB Object Librarian 43.5 MPLAB Assembler, Linker and Librarian for Various Device Families 43.6 MPLAB X SIM Software Simulator 43.7 MPLAB REAL ICE In-Circuit Emulator System 43.8 MPLAB ICD 3 In-Circuit Debugger System 43.9 PICkit 3 In-Circuit Debugger/ Programmer 43.10 MPLAB PM3 Device Programmer 43.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 43.12 Third-Party Development Tools 44.0 Electrical Characteristics 44.1 DC Characteristics Table 44-1: Operating MIPS vs. Voltage Table 44-2: Thermal Operating Conditions Table 44-3: Thermal Packaging Characteristics Table 44-4: DC Temperature and Voltage Specifications Table 44-5: Electrical Characteristics: RESETS TABLE 44-6: Low-Voltage Detect Characteristics Table 44-7: DC Characteristics: Operating Current (Idd = Iddio + Iddcore) Table 44-8: DC Characteristics: Idle Current (Iidle) Table 44-9: DC Characteristics: Power-Down Current (Ipd) Table 44-10: DC Characteristics: I/O Pin Input Specifications Table 44-11: DC Characteristics: I/O Pin Output Specifications (Continued) Table 44-12: DC Characteristics: I/O Pin Input Injection current Specifications Table 44-13: DDR2 SDRAM Controller I/O Specifications Table 44-14: SD Host Controller I/O Specifications Table 44-15: DC Characteristics: Program Memory(3) Table 44-16: DC Characteristics: Program Flash Memory Wait States Table 44-17: DC Characteristics: DDR2 SDRAM Memory Table 44-18: Comparator Specifications Table 44-19: Comparator Voltage Reference Specifications TABLE 44-20: CTMU Current Source Specifications Table 44-21: GLCD Controller DC Specifications 44.2 AC Characteristics and Timing Parameters Figure 44-1: Load Conditions for Device Timing Specifications Table 44-22: Capacitive Loading Requirements on Output Pins Figure 44-2: External Clock Timing Table 44-23: External Clock Timing Requirements Table 44-24: System Timing Requirements Table 44-25: SPLL Clock Timing Specifications Table 44-26: MPLL Clock Timing Requirements Table 44-27: Internal FRC Accuracy Table 44-28: Internal LPRC Accuracy Table 44-29: Internal Backup FRC (BFRC) Accuracy Figure 44-3: I/O Timing Characteristics Table 44-30: I/O Timing Requirements (Continued) Figure 44-4: Power-On Reset Timing Characteristics Figure 44-5: External Reset Timing Characteristics Table 44-31: Resets Timing Figure 44-6: Timer1-Timer9 External Clock Timing Characteristics Table 44-32: Timer1 External Clock Timing Requirements(1) Table 44-33: Timer2-Timer9 External Clock Timing Requirements Figure 44-7: Input Capture (CAPx) Timing Characteristics Table 44-34: Input Capture Module Timing Requirements Figure 44-8: Output Compare Module (OCx) Timing Characteristics Table 44-35: Output Compare Module Timing Requirements Figure 44-9: OCx/PWM Module Timing Characteristics Table 44-36: Simple OCx/PWM Mode Timing Requirements Figure 44-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics Table 44-37: SPIx Master Mode (CKE = 0) Timing Requirements Figure 44-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics Table 44-38: SPIx Module Master Mode (CKE = 1) Timing Requirements Figure 44-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics Table 44-39: SPIx Module Slave Mode (CKE = 0) Timing Requirements (Continued) Figure 44-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics Table 44-40: SPIx Module Slave Mode (CKE = 1) Timing Requirements (‘x’ = 1, 3, 4, 6) Figure 44-14: SQI Serial Input Timing Characteristics Figure 44-15: SQI Serial Output Timing Characteristics Table 44-41: SQI Timing Requirements Figure 44-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode) Figure 44-17: I2Cx Bus Data Timing Characteristics (Master Mode) Table 44-42: I2Cx Bus Data Timing Requirements (Master Mode) (Continued) Figure 44-18: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode) Figure 44-19: I2Cx Bus Data Timing Characteristics (Slave Mode) Table 44-43: I2Cx Bus Data Timing Requirements (Slave Mode) (Continued) Figure 44-20: CANx Module I/O Timing Characteristics Table 44-44: CANx Module I/O Timing Requirements Table 44-45: ADC Module Specifications Table 44-46: Analog-to-Digital Conversion Timing Requirements Table 44-47: ADC Sample Times with CVD Enabled Table 44-48: TEMPERATURE SENSOR SPECIFICATIONS Figure 44-21: Parallel Slave Port Timing Table 44-49: Parallel Slave Port Requirements Figure 44-22: Parallel Master Port Read Timing Diagram Table 44-50: Parallel Master Port Read Timing Requirements Figure 44-23: Parallel Master Port Write Timing Diagram Table 44-51: Parallel Master Port Write Timing Requirements Table 44-52: USB OTG Electrical Specifications Table 44-53: Ethernet Module Specifications Figure 44-24: MDIO Sourced by the PIC32 Device Figure 44-25: MDIO Sourced by the PHY Figure 44-26: Transmit Signal Timing Relationships at the MII Figure 44-27: Receive Signal Timing Relationships at the MII Figure 44-28: EBI Page Read Timing Figure 44-29: EBI Write Timing Table 44-54: EBI Timing Requirements Table 44-55: GLCD Controller Timing Specifications TABLE 44-56: DDR2 SDRAM Controller Timing Specifications Table 44-57: SD Host Controller Default Mode Timing Specifications Table 44-58: SD Host Controller High-Speed Mode Timing Specifications Figure 44-30: EJTAG Timing Characteristics Table 44-59: EJTAG Timing Requirements 45.0 AC and DC Characteristics Graphs FIGURE 45-1: Voh – 4x Driver Pins FIGURE 45-2: Vol – 4x Driver Pins FIGURE 45-3: Voh – 8x Driver Pins FIGURE 45-4: Vol – 8x Driver Pins FIGURE 45-5: Voh – 12x Driver Pins FIGURE 45-6: Vol – 12x Driver Pins FIGURE 45-7: Typical Temperature Sensor Voltage 46.0 Packaging Information 46.1 Package Marking Information 46.2 Package Details Appendix A: Revision History TABLE A-1: Major Section Updates (Continued) TABLE A-2: Major Section Updates (Continued) TABLE A-3: Major Section Updates TABLE A-4: Major Section Updates INDEX AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
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