Datasheet ADXRS453 (Analog Devices) - 19
| Manufacturer | Analog Devices |
| Description | High Performance, Digital Output Gyroscope |
| Pages / Page | 33 / 19 — ADXRS453. Data Sheet. FAULT REGISTER BIT DEFINITIONS. UV Bit. PLL Bit. … |
| Revision | B |
| File Format / Size | PDF / 833 Kb |
| Document Language | English |
ADXRS453. Data Sheet. FAULT REGISTER BIT DEFINITIONS. UV Bit. PLL Bit. Table 14. Fault Register Bit Definitions. Register Bit
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ADXRS453 Data Sheet FAULT REGISTER BIT DEFINITIONS UV Bit
Table 14 describes the bits available for signaling faults to The UV fault bit is asserted if the internally regulated voltage the user. The individual bits of the fault registers are updated (nominally 3 V) is observed to be less than 2.77 V. This mea- asynchronously, depending on their respective detection criteria; surement is low-pass filtered to prevent artifacts such as noise however, it is recommended that the fault registers be read at a spikes from asserting a fault condition. When a UV fault occurs, rate of at least 250 Hz. When asserted, an individual status bit the PWR fault bit is asserted simultaneously. Because the UV is not deasserted until it is read by the master device. If the error fault bit is not transmitted as part of a sensor data response, it is persists after a fault register read, the status bit is immediately recommended that the user read back the FAULT1 and FAULT0 reasserted and remains asserted until the next sequential memory registers upon the assertion of a PWR error to determine command/response exchange. The bits in the FAULT0 register are the specific error condition. appended to every sensor data response (see Table 10). Both
PLL Bit
fault registers can be accessed by issuing a read command to The PLL bit indicates that the device has experienced a failure Address 0x0A. in the phase-locked loop functional circuit block. This occurs
Table 14. Fault Register Bit Definitions
when the PLL fails to achieve synchronization with the resonator
Register Bit Name Description
structure. If the PLL status flag is active, the ST[1:0] bits of the FAULT1 Fail Failure that sets the ST[1:0] bits to 00 sensor data response are set to 00, indicating that the response AMP Amplitude detection failure contains potentially invalid rate data. OV Regulator overvoltage
Q Bit
UV Regulator undervoltage A Q fault is asserted based on two independent quadrature FAULT0 PLL Phase-locked loop failure calculations. Q Quadrature error NVM Nonvolatile memory fault The quad memory register (Address 0x08) contains a value POR Power-on or reset failed to initialize corresponding to the total instantaneous quadrature present PWR in the device. If this value exceeds 4096 LSB, a Q fault is Power regulation failed due to over- voltage or undervoltage condition issued. CST Continuous self-test failure or amplitude An internal quadrature accumulator records the amount detection failed of quadrature correction performed by the ADXRS453. A CHK Check: generate faults Q fault is issued when the quadrature error present in the
Fail Bit
device has contributed to an equivalent of 4°/sec (typical) of rate offset. The fail flag is asserted when the ST[1:0] bits are set to 00 (see the ST1 and ST0 Bits section). Assertion of the fail bit indicates
NVM Bit
that the device has experienced a gross failure and that the sensor An NVM error is transmitted to the control module when the data could be invalid. internal nonvolatile memory data fails a checksum calculation.
AMP Bit
This check is performed once every 50 μs and does not include The AMP fault bit is asserted when the measured amplitude the PIDx memory registers. of the silicon resonator has been significantly reduced. This
POR Bit
condition can occur if the voltage supplied to CP5 falls below An internal check is performed on device startup to ensure that the requirements of the internal voltage regulator. This fault bit the volatile memory of the device is functional. This is accom- is OR’ed with the CST fault bit; therefore, during a sensor data plished by programming a known value from the device ROM request, the CST bit position represents either an AMP failure into a volatile memory register. This value is then continuously or a CST failure. The full fault register can be read from memory compared to the known value in ROM every 1 μs for the duration to determine the specific failure. of the device operation. If the value stored in the volatile memory
OV Bit
changes or does not match the value stored in ROM, the POR The OV fault bit is asserted if the internally regulated voltage error flag is asserted. The value stored in ROM is rewritten to (nominally 3 V) is observed to exceed 3.3 V. This measurement the volatile memory upon a device power cycle. is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When an OV fault occurs, the PWR fault bit is asserted simultaneously. Because the OV fault bit is not transmitted as part of a sensor data response, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error to determine the specific error condition. Rev. B | Page 18 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide
ADXRS453 Data Sheet FAULT REGISTER BIT DEFINITIONS UV Bit
Table 14 describes the bits available for signaling faults to The UV fault bit is asserted if the internally regulated voltage the user. The individual bits of the fault registers are updated (nominally 3 V) is observed to be less than 2.77 V. This mea- asynchronously, depending on their respective detection criteria; surement is low-pass filtered to prevent artifacts such as noise however, it is recommended that the fault registers be read at a spikes from asserting a fault condition. When a UV fault occurs, rate of at least 250 Hz. When asserted, an individual status bit the PWR fault bit is asserted simultaneously. Because the UV is not deasserted until it is read by the master device. If the error fault bit is not transmitted as part of a sensor data response, it is persists after a fault register read, the status bit is immediately recommended that the user read back the FAULT1 and FAULT0 reasserted and remains asserted until the next sequential memory registers upon the assertion of a PWR error to determine command/response exchange. The bits in the FAULT0 register are the specific error condition. appended to every sensor data response (see Table 10). Both
PLL Bit
fault registers can be accessed by issuing a read command to The PLL bit indicates that the device has experienced a failure Address 0x0A. in the phase-locked loop functional circuit block. This occurs
Table 14. Fault Register Bit Definitions
when the PLL fails to achieve synchronization with the resonator
Register Bit Name Description
structure. If the PLL status flag is active, the ST[1:0] bits of the FAULT1 Fail Failure that sets the ST[1:0] bits to 00 sensor data response are set to 00, indicating that the response AMP Amplitude detection failure contains potentially invalid rate data. OV Regulator overvoltage
Q Bit
UV Regulator undervoltage A Q fault is asserted based on two independent quadrature FAULT0 PLL Phase-locked loop failure calculations. Q Quadrature error NVM Nonvolatile memory fault The quad memory register (Address 0x08) contains a value POR Power-on or reset failed to initialize corresponding to the total instantaneous quadrature present PWR in the device. If this value exceeds 4096 LSB, a Q fault is Power regulation failed due to over- voltage or undervoltage condition issued. CST Continuous self-test failure or amplitude An internal quadrature accumulator records the amount detection failed of quadrature correction performed by the ADXRS453. A CHK Check: generate faults Q fault is issued when the quadrature error present in the
Fail Bit
device has contributed to an equivalent of 4°/sec (typical) of rate offset. The fail flag is asserted when the ST[1:0] bits are set to 00 (see the ST1 and ST0 Bits section). Assertion of the fail bit indicates
NVM Bit
that the device has experienced a gross failure and that the sensor An NVM error is transmitted to the control module when the data could be invalid. internal nonvolatile memory data fails a checksum calculation.
AMP Bit
This check is performed once every 50 μs and does not include The AMP fault bit is asserted when the measured amplitude the PIDx memory registers. of the silicon resonator has been significantly reduced. This
POR Bit
condition can occur if the voltage supplied to CP5 falls below An internal check is performed on device startup to ensure that the requirements of the internal voltage regulator. This fault bit the volatile memory of the device is functional. This is accom- is OR’ed with the CST fault bit; therefore, during a sensor data plished by programming a known value from the device ROM request, the CST bit position represents either an AMP failure into a volatile memory register. This value is then continuously or a CST failure. The full fault register can be read from memory compared to the known value in ROM every 1 μs for the duration to determine the specific failure. of the device operation. If the value stored in the volatile memory
OV Bit
changes or does not match the value stored in ROM, the POR The OV fault bit is asserted if the internally regulated voltage error flag is asserted. The value stored in ROM is rewritten to (nominally 3 V) is observed to exceed 3.3 V. This measurement the volatile memory upon a device power cycle. is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When an OV fault occurs, the PWR fault bit is asserted simultaneously. Because the OV fault bit is not transmitted as part of a sensor data response, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error to determine the specific error condition. Rev. B | Page 18 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide
