Datasheet KSZ8765CLX (Microchip)

DescriptionIntegrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces
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KSZ8765CLX. Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/. RMII Interfaces

Datasheet KSZ8765CLX Microchip

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KSZ8765CLX Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces Target Applications
• Robust PHY Ports - Four Integrated IEEE 802.3/802.3u-Compli- • Industrial Ethernet Applications that Employ IEEE ant Ethernet Transceivers; Port 1 and Port 2 802.3-Compliant MACs. (Ethernet/IP, Profinet, Support 100Base-FX, Port 3 and Port 4 Sup- MODBUS TCP, etc.) port 10/100Base-T/TX • VoIP Phone - 802.1az EEE Supported • Set-Top/Game Box - On-Chip Termination Resistors and Internal • Automotive Biasing for Differential Pairs to Reduce • Industrial Control Power • IPTV POF - HP Auto MDI/MDI-X Crossover Support Elim- • SOHO Residential Gateway with Full-Wire Speed inates the Need to Differentiate Between of Four LAN Ports Straight or Crossover Cables in Applications • Broadband Gateway/Firewall/VPN • MAC and GMAC Ports • Integrated DSL/Cable Modem - Four Internal Media Access Control (MAC1 to • Wireless LAN Access Point + Gateway MAC4) Units and One Internal Gigabit Media • Standalone 10/100 Switch Access Control (GMAC5) Unit - GMII, RGMII, MII, or RMII Interfaces Support • Networked Measurement and Control Systems for the Port 5 GMAC5 with Uplink - 2 KByte Jumbo Packet Support
- Tail Tagging Mode (One Byte Added Before • Management Capabilities FCS) Support on Port 5 to Inform the Proces- - The KSZ8765CLX Includes All the Functions sor in which the Ingress Port Receives the of a 10/100BASE-T/TX Switch System Which Packet and its Priority Combines a Switch Engine, Frame Buffer - Supports Reduced Media Independent Inter- Management, Address Look-Up Table, face (RMII) with 50 MHz Reference Clock Queue Management, MIB Counters, Media Output Access Controllers (MAC), and PHY Trans- - Supports Media Independent Interface (MII) ceivers in Either PHY Mode or MAC Mode on Port 5 - Non-Blocking Store-and-Forward Switch - LinkMD® Cable Diagnostic Capabilities for Fabric Assures Fast Packet Delivery by Uti- Determining Cable Opens, Shorts, and lizing a 1024-Entries Forwarding Table Length - Port Mirroring/Monitoring/Sniffing: Ingress • Advanced Switch Capabilities and/or Egress Traffic to Any Port - Non-Blocking Store-and-Forward Switch - MIB Counters for Fully-Compliant Statistics Fabric Assures Fast Packet Delivery by Uti- Gathering (36 Counters per Port) lizing 1024 Entry Forwarding Table - Support Hardware for Port-Based Flush and - 64 KB Frame Buffer RAM Freeze Command in MIB Counter. - IEEE 802.1q VLAN Support for up to 128 - Multiple Loopback of Remote, PHY, and MAC Active VLAN Groups (Full-Range 4096 of Modes Support for the Diagnostics VLAN IDs) - Rapid Spanning Tree Support (RSTP) for - IEEE 802.1p/Q Tag Insertion or Removal on Topology Management and Ring/Linear a Per Port Basis (Egress) Recovery - VLAN ID Tag/Untag Options on Per Port Basis - Fully Compliant with IEEE 802.3/802.3u Standards - IEEE 802.3x Full-Duplex with Force-Mode  2016 Microchip Technology Inc.

DS00002130A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines