Datasheet KSZ8765CLX (Microchip) - 10
| Manufacturer | Microchip |
| Description | Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces |
| Pages / Page | 131 / 10 — KSZ8765CLX. TABLE 2-1:. SIGNALS - KSZ8765CLX (CONTINUED). Pin. Type. … |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
KSZ8765CLX. TABLE 2-1:. SIGNALS - KSZ8765CLX (CONTINUED). Pin. Type. Port. Description. Number. Name. Note 2-1. Note:
Model Line for this Datasheet
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KSZ8765CLX TABLE 2-1: SIGNALS - KSZ8765CLX (CONTINUED) Pin Pin Type Port Description Number Name Note 2-1
62 LED2_1 Ipu/O 2 Port 2 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: Port 5 GMII/MII and RMII mode select When Port 5 is GMII/MII mode: PU = GMII/MII is in GMAC/MAC mode. (Default) PD = GMII/MII is in GPHY/PHY mode.
Note:
When set GMAC5 GMII to GPHY mode, the CRS and COL pins will change from the input to output. When set MII to PHY mode, the CRS, COL, RXC and TXC pins will change from the input to output. When Port 5 is RMII mode: PU = Clock mode in RMII, using 25 MHz OSC clock and provide 50 MHz RMII clock from pin RXC5. PD = Normal mode in RMII, the TXC5/REFCLKI5 pin on the port 5 RMII will receive an external 50 MHz clock
Note:
Port 5 also can use either an internal or external clock in RMII mode based on this strap pin or the setting of the Register 86 (0x56) bit[7]. 63 LED2_0 Ipu/O 2 Port 2 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: REFCLKO enable PU = REFCLK_O (25 MHz) is enabled. (Default) PD = REFCLK_O is disabled.
Note:
It is better to disable this 25 MHz clock if not providing an extra 25 MHz clock for the system. 64 LED1_1 Ipu/O 1 Port 1 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: PLL Clock source select PU = Still use 25 MHz clock from XI/XO pin even though it is in Port 5 RMII normal mode. PD = Use external clock from pin TXC5 in Port 5 RMII normal mode.
Note:
If received clock in Port 5 RMII normal mode has large clock jitter, one can select the 25 MHz crystal/oscillator as the switch’s clock source. 65 LED1_0 Ipu/O 1 Port 1 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: Speed select in GMII/RGMII PU = 1 Gbps in GMII/RGMII.(Default) PD = 10/100 Mbps in GMII/RGMII.
Note:
Programmable through internal registers also. 66 SPIQ Ipd/O All SPI Serial Data Output in SPI Slave Mode: Strap Option: Serial bus configuration. PD = SPI slave mode. PU = MDC/MDIO mode.
Note:
An external pull-up or pull-down resistor is required. 67 SCL_MDC Ipu All Clock Input for SPI or MDC/MDIO Interface: Input clock up to 50 MHz in SPI slave mode. Input clock up to 25 MHz in MDC/MDIO for MIIM access. DS00002130A-page 10
2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
62 LED2_1 Ipu/O 2 Port 2 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: Port 5 GMII/MII and RMII mode select When Port 5 is GMII/MII mode: PU = GMII/MII is in GMAC/MAC mode. (Default) PD = GMII/MII is in GPHY/PHY mode.
Note:
When set GMAC5 GMII to GPHY mode, the CRS and COL pins will change from the input to output. When set MII to PHY mode, the CRS, COL, RXC and TXC pins will change from the input to output. When Port 5 is RMII mode: PU = Clock mode in RMII, using 25 MHz OSC clock and provide 50 MHz RMII clock from pin RXC5. PD = Normal mode in RMII, the TXC5/REFCLKI5 pin on the port 5 RMII will receive an external 50 MHz clock
Note:
Port 5 also can use either an internal or external clock in RMII mode based on this strap pin or the setting of the Register 86 (0x56) bit[7]. 63 LED2_0 Ipu/O 2 Port 2 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: REFCLKO enable PU = REFCLK_O (25 MHz) is enabled. (Default) PD = REFCLK_O is disabled.
Note:
It is better to disable this 25 MHz clock if not providing an extra 25 MHz clock for the system. 64 LED1_1 Ipu/O 1 Port 1 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: PLL Clock source select PU = Still use 25 MHz clock from XI/XO pin even though it is in Port 5 RMII normal mode. PD = Use external clock from pin TXC5 in Port 5 RMII normal mode.
Note:
If received clock in Port 5 RMII normal mode has large clock jitter, one can select the 25 MHz crystal/oscillator as the switch’s clock source. 65 LED1_0 Ipu/O 1 Port 1 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: Speed select in GMII/RGMII PU = 1 Gbps in GMII/RGMII.(Default) PD = 10/100 Mbps in GMII/RGMII.
Note:
Programmable through internal registers also. 66 SPIQ Ipd/O All SPI Serial Data Output in SPI Slave Mode: Strap Option: Serial bus configuration. PD = SPI slave mode. PU = MDC/MDIO mode.
Note:
An external pull-up or pull-down resistor is required. 67 SCL_MDC Ipu All Clock Input for SPI or MDC/MDIO Interface: Input clock up to 50 MHz in SPI slave mode. Input clock up to 25 MHz in MDC/MDIO for MIIM access. DS00002130A-page 10
2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
