Datasheet KSZ8775CLX (Microchip) - 28
| Manufacturer | Microchip |
| Description | Integrated 5–Port 10/100 Managed Ethernet Switch with Port 4 RMII and Port 5 RGMII/MII/ RMII Interfaces |
| Pages / Page | 132 / 28 — KSZ8775CLX. 3.5.3.1. 3.5.3.1.1 Configuration Interface |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
KSZ8775CLX. 3.5.3.1. 3.5.3.1.1 Configuration Interface
Model Line for this Datasheet
Text Version of Document
KSZ8775CLX
3.5.3.1
3.5.3.1.1 Configuration Interface
SPI Slave Serial Bus Configuration The KSZ8775CLX can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including
“VLAN,” “IGMP snooping,” “MIB counters,” etc. The external SPI master device can access any registers randomly in
the datasheet shown. The SPI mode can configure all the desired settings including indirect registers and tables.
KSZ8775 default is in the ‘start switch’ mode with the register 1 bit [0] =’1’, to disable the switch, write a "0" to Register
1 bit [0].
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KSZ8775CLX also supports multiple reads or writes. After a byte is written to or read from the
KSZ8775CLX, the internal address counter automatically increments if the SPI slave select signal (SPIS_N) continues
to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on
SPIQ. If SPIS_N is kept low after the first byte is written, then bits on the master out slave input (SPID) line will be written
to the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal
must be asserted high and then low again before issuing another command and address. The address counter wraps
back to zero once it reaches the highest address. Therefore, the entire register set can be written to or read from by
issuing a single command and address.
The KSZ8775CLX is able to support a SPI bus up to 50MHz. A high performance SPI master is recommended to prevent internal counter overflow.
To use the KSZ8775CLX SPI:
1. At the board level, connect the KSZ8775CLX pins as shown in Table 3-5. TABLE 3-5: 2.
3.
4. SPI CONNECTIONS
KSZ8775CLX Signal Name Microprocessor Signal Description SPIS_N (S_CS) SPI slave select SCL (S_CLK) SPI clock SDA (S_DI) Master out. Slave input. SPIQ (S_DO) Master input. Slave output. Configure the serial communication to SPI slave mode by pulling down pin SPIQ with a pull-down resistor.
Write configuration data to registers using a typical SPI write data cycle as shown in Figure 3-7 or SPI multiple
write as shown in Figure 3-8. Note that data input on SDA is registered on the rising edge of SCL clock.
Registers can be read and the configuration can be verified with a typical SPI read data cycle as shown in
Figure 3-7 or a multiple read as shown in Figure 3-8. Note that read data is registered out of SPIQ on the falling
edge of SCL clock. DS00002129C-page 28 2015 Microchip Technology Inc.
3.5.3.1
3.5.3.1.1 Configuration Interface
SPI Slave Serial Bus Configuration The KSZ8775CLX can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including
“VLAN,” “IGMP snooping,” “MIB counters,” etc. The external SPI master device can access any registers randomly in
the datasheet shown. The SPI mode can configure all the desired settings including indirect registers and tables.
KSZ8775 default is in the ‘start switch’ mode with the register 1 bit [0] =’1’, to disable the switch, write a "0" to Register
1 bit [0].
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KSZ8775CLX also supports multiple reads or writes. After a byte is written to or read from the
KSZ8775CLX, the internal address counter automatically increments if the SPI slave select signal (SPIS_N) continues
to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on
SPIQ. If SPIS_N is kept low after the first byte is written, then bits on the master out slave input (SPID) line will be written
to the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal
must be asserted high and then low again before issuing another command and address. The address counter wraps
back to zero once it reaches the highest address. Therefore, the entire register set can be written to or read from by
issuing a single command and address.
The KSZ8775CLX is able to support a SPI bus up to 50MHz. A high performance SPI master is recommended to prevent internal counter overflow.
To use the KSZ8775CLX SPI:
1. At the board level, connect the KSZ8775CLX pins as shown in Table 3-5. TABLE 3-5: 2.
3.
4. SPI CONNECTIONS
KSZ8775CLX Signal Name Microprocessor Signal Description SPIS_N (S_CS) SPI slave select SCL (S_CLK) SPI clock SDA (S_DI) Master out. Slave input. SPIQ (S_DO) Master input. Slave output. Configure the serial communication to SPI slave mode by pulling down pin SPIQ with a pull-down resistor.
Write configuration data to registers using a typical SPI write data cycle as shown in Figure 3-7 or SPI multiple
write as shown in Figure 3-8. Note that data input on SDA is registered on the rising edge of SCL clock.
Registers can be read and the configuration can be verified with a typical SPI read data cycle as shown in
Figure 3-7 or a multiple read as shown in Figure 3-8. Note that read data is registered out of SPIQ on the falling
edge of SCL clock. DS00002129C-page 28 2015 Microchip Technology Inc.
