Datasheet KSZ8863MLL, KSZ8863FLL, KSZ8863RLL (Microchip)

DescriptionIntegrated 3-Port 10/100 Managed Switch with PHYs
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KSZ8863MLL/FLL/RLL. Integrated 3-Port 10/100 Managed Switch. with PHYs. Features. Applications

Datasheet KSZ8863MLL, KSZ8863FLL, KSZ8863RLL Microchip

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KSZ8863MLL/FLL/RLL Integrated 3-Port 10/100 Managed Switch with PHYs Features
- Non-Blocking Switch Fabric Ensures Fast Packet Delivery by Utilizing a 1k MAC Address • Advanced Switch Features Lookup Table and a Store-and-Forward Archi- - IEEE 802.1q VLAN Support for Up to 16 Groups tecture (Full Range of VLAN IDs) - Full-Duplex IEEE 802.3x Flow Control (PAUSE) - VLAN ID Tag/Untag Options, Per Port Basis with Force Mode Option - IEEE 802.1p/q Tag Insertion or Removal on a - Half-Duplex Back Pressure Flow Control Per Port Basis (Egress) - HP Auto MDI-X for Reliable Detection of and - Programmable Rate Limiting at the Ingress and Correction for Straight-Through and Crossover Egress on a Per Port Basis Cables with Disable and Enable Option - Broadcast Storm Protection with Percent Con- - LinkMD® TDR-Based Cable Diagnostics Permit trol (Global and Per Port Basis) Identification of Faulty Copper Cabling - IEEE 802.1d Rapid Spanning Tree Protocol - MII Interface Supports Both MAC Mode and Support PHY Mode - Tail Tag Mode (1 byte Added before FCS) Sup- - Comprehensive LED Indicator Support for Link, port at Port 3 to Inform the Processor which Activity, Full-/Half-Duplex and 10/100 Speed Ingress Port Receives the Packet and its Prior- - HBM ESD Rating 4 kV ity • Switch Monitoring Features - Bypass Feature that Automatically Sustains the - Port Mirroring/Monitoring/Sniffing: Ingress and/ Switch Function between Port 1 and Port 2 or Egress Traffic to Any Port or MII when CPU (Port 3 Interface) Goes to the Sleep - MIB Counters for Ful y Compliant Statistics Mode Gathering 34 MIB Counters Per Port - Self-Address Filtering - Loopback Modes for Remote Diagnostic of Fail- - Individual MAC Address for Port 1 and Port 2 ure - Supports RMII Interface and 50 MHz Reference • Low Power Dissipation Clock Output - Full-Chip Software Power-Down (Register Con- - IGMP Snooping (IPv4) Support for Multicast figuration Not Saved) Packet Filtering - Energy-Detect Mode Support - IPv4/IPv6 QoS Support - Dynamic Clock Tree Shutdown Feature - MAC Filtering Function to Forward Unknown - Per Port Based Software Power-Save on PHY Unicast Packets to Specified Port (Idle Link Detection, Register Configuration Pre- • Comprehensive Configuration Register Access served) - Serial Management Interface (SMI) to All Inter- - Voltages: Single 3.3V Supply with Internal 1.8V nal Registers LDO for 3.3V VDDIO - MII Management (MIIM) Interface to PHY Reg- - Optional 3.3V, 2.5V, and 1.8V for VDDIO isters - Transceiver Power 3.3V for VDDA_3.3 - High Speed SPI and I2C Interface to All Internal • Industrial Temperature Range: –40°C to +85°C Registers • Available in a 48-Pin LQFP, Lead-Free Package - I/O Pins Strapping and EEPROM to Program Selective Registers in Unmanaged Switch Mode
- Control Registers Configurable on the Fly (Port- • VoIP Phone Priority, 802.1p/d/q, AN…) • Set-Top/Game Box • QoS/CoS Packet Prioritization Support • Automotive - Per Port, 802.1p and DiffServ-Based • Industrial Control - Re-Mapping of 802.1p Priority Field Per Port • IPTV POF basis, Four Priority Levels • SOHO Residential Gateway • Proven Integrated 3-Port 10/100 Ethernet Switch • Broadband Gateway/Firewall/VPN - 3rd Generation Switch with Three MACs and • Integrated DSL/Cable Modem Two PHYs Fully Compliant with IEEE 802.3u • Wireless LAN Access Point + Gateway Standard • Standalone 10/100 Switch  2017 Microchip Technology Inc.

DS00002335B-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Timing 7.7 Auto-Negotiation Timing 7.8 MDC/MDIO Timing 7.9 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
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