Datasheet KSZ8863MLL, KSZ8863FLL, KSZ8863RLL (Microchip) - 5

KSZ8863MLL/FLL/RLL 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 48-PIN 7 MM X 7 MM LQFP ASSIGNMENT, (TOP VIEW)
FXSD1 RSTN P2LED0 P2LED1 P1LED0 P1LED1 VDDCO GND VDDIO SPISN SPIQ SDA_MDIO 48 47 46 45 44 43 42 41 40 39 38 37 RXM1 1 36 SCL_MDC RXP1 2 35 INTRN TXM1 3 34 SCRS3 TXP1 4 33 SCOL3 VDDA_3.3 5 32 VDDC ISET 6 48-pin 31 GND VDDA_1.8 7 LQFP 30 SMRXC3 RXM2 8 29 SMRXD30 RXP2 9 28 SMRXD31 AGND 10 27 SMRXD32 TXM2 11 26 SMRXD33/REFCLKO_3 TXP2 12 25 SMRXDV3 13 14 15 16 17 18 19 20 21 22 23 24 X1 NC X2 GND VDDIO SMTXEN3 SMTXD32 SMTXD31 SMTXD30 SMTXC3/REFCLKI_3 SMTXER3/MII_LINK_3 SMTXD33/EN_REFCLKO_3  2017 Microchip Technology Inc.

DS00002335B-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Timing 7.7 Auto-Negotiation Timing 7.8 MDC/MDIO Timing 7.9 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service