Datasheet KSZ8863MLL, KSZ8863FLL, KSZ8863RLL (Microchip) - 8
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 92 / 8 — KSZ8863MLL/FLL/RLL. TABLE 2-1:. SIGNALS (CONTINUED). Pin. Type. … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
KSZ8863MLL/FLL/RLL. TABLE 2-1:. SIGNALS (CONTINUED). Pin. Type. Description. Number. Name. Note 2-1. Port 1 LED Indicators:. Strap option:
Model Line for this Datasheet
Text Version of Document
KSZ8863MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Type Description Number Name Note 2-1
SPI Slave mode: chip select (active-low) When SPISN is high, KSZ8863MLL/FLL/RLL is deselected and SPIQ is held in a high impedance state. 39 SPISN Ipd A high-to-low transition is used to initiate SPI data transfer. Note: An external pull-up is needed on this pin when using SPI or MDC/ MDIO-MIIM/SMI mode. 3.3V, 2.5V, or 1.8V digital V 40 VDDIO P DD input power supply for IO with well decou- pling capacitors 41 GND GND Digital ground 1.8V core power voltage output (internal 1.8V LDO regulator output) This 1.8V output pin provides power to both VDDA_1.8 and VDDC input pins. 42 VDDCO P Note: Internally, 1.8V LDO regulator input comes from VDDIO. Do not con- nect an external power supply to VDDCO pin. The ferrite bead is requested between analog and digital 1.8V core power.
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit [5:4]) 43 P1LED1 Ipu/O
Strap option:
Force the speed on port 1 (P1SPD) PU = Force port 1 to 100BT if P1ANEN = 0 PD = Force port 1 to 10BT if P1ANEN = 0
Port 1 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4]) 44 P1LED0 Ipd/O
Strap option:
Enable auto-negotiation on port 1 (P1ANEN) PU = Enable (better to pull up in design) PD = Disable (default) DS00002335B-page 8
2017 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Timing 7.7 Auto-Negotiation Timing 7.8 MDC/MDIO Timing 7.9 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
SPI Slave mode: chip select (active-low) When SPISN is high, KSZ8863MLL/FLL/RLL is deselected and SPIQ is held in a high impedance state. 39 SPISN Ipd A high-to-low transition is used to initiate SPI data transfer. Note: An external pull-up is needed on this pin when using SPI or MDC/ MDIO-MIIM/SMI mode. 3.3V, 2.5V, or 1.8V digital V 40 VDDIO P DD input power supply for IO with well decou- pling capacitors 41 GND GND Digital ground 1.8V core power voltage output (internal 1.8V LDO regulator output) This 1.8V output pin provides power to both VDDA_1.8 and VDDC input pins. 42 VDDCO P Note: Internally, 1.8V LDO regulator input comes from VDDIO. Do not con- nect an external power supply to VDDCO pin. The ferrite bead is requested between analog and digital 1.8V core power.
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit [5:4]) 43 P1LED1 Ipu/O
Strap option:
Force the speed on port 1 (P1SPD) PU = Force port 1 to 100BT if P1ANEN = 0 PD = Force port 1 to 10BT if P1ANEN = 0
Port 1 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4]) 44 P1LED0 Ipd/O
Strap option:
Enable auto-negotiation on port 1 (P1ANEN) PU = Enable (better to pull up in design) PD = Disable (default) DS00002335B-page 8
2017 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Timing 7.7 Auto-Negotiation Timing 7.8 MDC/MDIO Timing 7.9 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
