Datasheet LTC1871 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Wide Input Range, No RSENSE Current Mode Boost, Flyback and SEPIC Controller |
| Pages / Page | 36 / 8 — BLOCK DIAGRAM. OPERATION. Main Control Loop |
| File Format / Size | PDF / 534 Kb |
| Document Language | English |
BLOCK DIAGRAM. OPERATION. Main Control Loop
Model Line for this Datasheet
Text Version of Document
LTC1871
BLOCK DIAGRAM
RUN + 1 BIAS AND SLOPE START-UP C2 COMPENSATION CONTROL – 1.248V FREQ VIN 4 V-TO-I OSC 9 0.6V MODE/SYNC IOSC INTVCC 5 GATE PWM LATCH 50k LOGIC 7 85mV S + – OV 1.230V Q R GND + BURST CURRENT SENSE COMPARATOR COMPARATOR + 0.30V + 10 FB – EA C1 – 3 – gm + 1.230V ITH 2 V-TO-I INTV R CC I LOOP LOOP 5.2V 8 LDO 1.230V SLOPE 1.230V UV – TO GND START-UP BIAS VREF 6 + CONTROL 1871 BD 2.00V VIN
OPERATION Main Control Loop
is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the The LTC1871 is a constant frequency, current mode con- latch. The divided-down output voltage is compared to an troller for DC/DC boost, SEPIC and fl yback converter ap- internal 1.230V reference by the error amplifi er EA, which plications. The LTC1871 is distinguished from conventional outputs an error signal at the I current mode controllers because the current control loop TH pin. The voltage on the I can be closed by sensing the voltage drop across the power TH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the FB voltage MOSFET switch instead of across a discrete sense resistor, relative to the reference voltage causes the I as shown in Figure 2. This sensing technique improves TH pin to rise, which causes the current comparator C1 to trip at a higher effi ciency, increases power density, and reduces the cost peak inductor current value. The average inductor current of the overall solution. will therefore rise until it equals the load current, thereby For circuit operation, please refer to the Block Diagram of maintaining output regulation. the IC and Figure 1. In normal operation, the power MOSFET 1871fe 8
BLOCK DIAGRAM
RUN + 1 BIAS AND SLOPE START-UP C2 COMPENSATION CONTROL – 1.248V FREQ VIN 4 V-TO-I OSC 9 0.6V MODE/SYNC IOSC INTVCC 5 GATE PWM LATCH 50k LOGIC 7 85mV S + – OV 1.230V Q R GND + BURST CURRENT SENSE COMPARATOR COMPARATOR + 0.30V + 10 FB – EA C1 – 3 – gm + 1.230V ITH 2 V-TO-I INTV R CC I LOOP LOOP 5.2V 8 LDO 1.230V SLOPE 1.230V UV – TO GND START-UP BIAS VREF 6 + CONTROL 1871 BD 2.00V VIN
OPERATION Main Control Loop
is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the The LTC1871 is a constant frequency, current mode con- latch. The divided-down output voltage is compared to an troller for DC/DC boost, SEPIC and fl yback converter ap- internal 1.230V reference by the error amplifi er EA, which plications. The LTC1871 is distinguished from conventional outputs an error signal at the I current mode controllers because the current control loop TH pin. The voltage on the I can be closed by sensing the voltage drop across the power TH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the FB voltage MOSFET switch instead of across a discrete sense resistor, relative to the reference voltage causes the I as shown in Figure 2. This sensing technique improves TH pin to rise, which causes the current comparator C1 to trip at a higher effi ciency, increases power density, and reduces the cost peak inductor current value. The average inductor current of the overall solution. will therefore rise until it equals the load current, thereby For circuit operation, please refer to the Block Diagram of maintaining output regulation. the IC and Figure 1. In normal operation, the power MOSFET 1871fe 8
