Datasheet ATtiny28L, ATtiny28V (Atmel) - 3
| Manufacturer | Atmel |
| Pages / Page | 81 / 3 — ATtiny28L/V. Pin Descriptions. VCC. GND. Port A (PA3..PA0). Port B … |
| File Format / Size | PDF / 680 Kb |
| Document Language | English |
ATtiny28L/V. Pin Descriptions. VCC. GND. Port A (PA3..PA0). Port B (PB7..PB0). Port D (PD7..PD0). XTAL1. XTAL2. RESET. Figure 2
Model Line for this Datasheet
Text Version of Document
link to page 27
ATtiny28L/V
rupt on low-level input feature enables the ATtiny28 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes. The device is manufactured using Atmel’s high-density, nonvolatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATtiny28 AVR is supported with a full suite of program and system development tools including: macro assemblers, pro- gram debugger/simulators, in-circuit emulators and evaluation kits.
Pin Descriptions VCC
Supply voltage pin.
GND
Ground pin.
Port A (PA3..PA0)
Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED driver. At V = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are CC bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri- stated when a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0)
Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B pins that are externally pulled low will source current if the pull-ups are activated. Port B also serves the functions of various special features of the ATtiny28 as listed on page 27. If any of the special features are enabled, the pull-up(s) on the corresponding pin(s) is automatically disabled. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 2. 3
1062F–AVR–07/06 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents
ATtiny28L/V
rupt on low-level input feature enables the ATtiny28 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes. The device is manufactured using Atmel’s high-density, nonvolatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATtiny28 AVR is supported with a full suite of program and system development tools including: macro assemblers, pro- gram debugger/simulators, in-circuit emulators and evaluation kits.
Pin Descriptions VCC
Supply voltage pin.
GND
Ground pin.
Port A (PA3..PA0)
Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED driver. At V = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are CC bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri- stated when a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0)
Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B pins that are externally pulled low will source current if the pull-ups are activated. Port B also serves the functions of various special features of the ATtiny28 as listed on page 27. If any of the special features are enabled, the pull-up(s) on the corresponding pin(s) is automatically disabled. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 2. 3
1062F–AVR–07/06 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents
