Datasheet ADE7763 (Analog Devices) - 6

ManufacturerAnalog Devices
DescriptionSingle-Phase Active and Apparent Energy Metering IC
Pages / Page56 / 6 — ADE7763. Data Sheet. TIMING CHARACTERISTICS. Table 2. Timing …
RevisionC
File Format / SizePDF / 841 Kb
Document LanguageEnglish

ADE7763. Data Sheet. TIMING CHARACTERISTICS. Table 2. Timing Characteristics1, 2. Parameter Spec Unit Test. Conditions/Comments

ADE7763 Data Sheet TIMING CHARACTERISTICS Table 2 Timing Characteristics1, 2 Parameter Spec Unit Test Conditions/Comments

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ADE7763 Data Sheet TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C.
Table 2. Timing Characteristics1, 2 Parameter Spec Unit Test Conditions/Comments
Write Timing t1 50 ns min CS falling edge to first SCLK falling edge. t2 50 ns min SCLK logic high pulse width. t3 50 ns min SCLK logic low pulse width. t4 10 ns min Valid data setup time before falling edge of SCLK. t5 5 ns min Data hold time after SCLK falling edge. t6 4 μs min Minimum time between the end of data byte transfers. t7 3200 ns min Minimum time between byte transfers during a serial write. t8 100 ns min) CS hold time after SCLK falling edge. Read Timing t 3 9 4 μs min Minimum time between read command (i.e., a write to communication register) and data read. t10 50 ns min Minimum time between data byte transfers during a multibyte read. t11 30 ns min Data access time after SCLK rising edge following a write to the communication register. t 4 12 100 ns max Bus relinquish time after falling edge of SCLK. 10 ns min t 5 13 100 ns max Bus relinquish time after rising edge of CS. 10 ns min 1 Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2 See Figure 3, Figure 4, and the Serial Interface section. 3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min. 4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
t8 CS t1 t t6 3 t t SCLK 7 7 t t 2 4 t5 DIN 1 0 A5 A4 A3 A2 A1 A0 DB7 DB0 DB7 DB0
-003
COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
04481-A Figure 3. Serial Write Timing
CS t1 t13 t9 t10 SCLK 0 DIN 0 A5 A4 A3 A2 A1 A0 t t t 11 11 12 DOUT DB7 DB0 DB7 DB0
-004
COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
04481-A Figure 4. Serial Read Timing Rev. C | Page 6 of 56 Document Outline Features General Description Functional Block Diagram Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Terminology Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs di/dt Current Sensor and Digital Integrator Zero-Crossing Detection Zero-Crossing Timeout Period Measurement Power Supply Monitor Line Voltage Sag Detection Sag Level Set Peak Detection Peak Level Set Peak Level Record Interrupts Using Interrupts with an MCU Interrupt Timing Temperature Measurement Analog-to-Digital Conversion Antialias Filter ADC Transfer Function Reference Circuit Channel 1 ADC Channel 1 Sampling Channel 1 RMS Calculation Channel 1 RMS Offset Compensation Channel 2 ADC Channel 2 Sampling Channel 2 RMS Calculation Channel 2 RMS Offset Compensation Phase Compensation Active Power Calculation Energy Calculation Integration Time under Steady Load Power Offset Calibration Energy-to-Frequency Conversion Line Cycle Energy Accumulation Mode Positive-Only Accumulation Mode No-Load Threshold Apparent Power Calculation Apparent Power Offset Calibration Apparent Energy Calculation Integration Times under Steady Load Line Apparent Energy Accumulation Energies Scaling Calibrating an Energy Meter Watt Gain Calibrating Watt Gain Using a Reference Meter Example Calibrating Watt Gain Using an Accurate Source Example Watt Offset Calibrating Watt Offset Using a Reference Meter Example Calibrating Watt Offset with an Accurate Source Example Phase Calibration Calibrating Phase Using a Reference Meter Example Calibrating Phase with an Accurate Source Example VRMS and IRMS Calibration Apparent Energy CLKIN Frequency Suspending Functionality Checksum Register Serial Interface ADE7763 Serial Write Operation Serial Read Operation Registers Register Descriptions Communication Register Mode Register (0x09) Outline Dimensions Ordering Guide CH1OS Register (0x0D) Outline Dimensions Ordering Guide
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