Datasheet LT1361, LT1362 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual and Quad 50MHz, 800V/µs Op Amps |
| Pages / Page | 12 / 10 — APPLICATIONS INFORMATION. tion with large, sustained differential inputs. … |
| File Format / Size | PDF / 236 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. tion with large, sustained differential inputs. Capacitive Loading. Power Dissipation
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LT1361/LT1362
U U W U APPLICATIONS INFORMATION tion with large, sustained differential inputs
. Under whereas the same output step in unity gain has a 10 times normal, closed-loop operation, an increase of power dis- greater input step. The curve of Slew Rate vs Input Level sipation is only noticeable in applications with large slewing illustrates this relationship. The LT1361/LT1362 are tested outputs and is proportional to the magnitude of the for slew rate in a gain of –2 so higher slew rates can be differential input voltage and the percent of the time that expected in gains of 1 and –1, and lower slew rates in the inputs are apart. Measure the average supply current higher gain configurations. for the application in order to calculate the power dissipa- The RC network across the output stage is bootstrapped tion. when the amplifier is driving a light or moderate load and has no effect under normal operation. When driving a
Capacitive Loading
capacitive load (or a low value resistive load) the network The LT1361/LT1362 are stable with any capacitive load. is incompletely bootstrapped and adds to the compensa- This is accomplished by sensing the load induced output tion at the high impedance node. The added capacitance pole and adding compensation at the amplifier gain node. slows down the amplifier which improves the phase As the capacitive load increases, both the bandwidth and margin by moving the unity-gain frequency away from the phase margin decrease so there will be peaking in the pole formed by the output impedance and the capacitive frequency domain and in the transient response as shown load. The zero created by the RC combination adds phase in the typical performance curves. The photo of the small to ensure that even for very large load capacitances, the signal response with 500pF load shows 60% peaking. The total phase lag can never exceed 180 degrees (zero phase large signal response shows the output slew rate being margin) and the amplifier remains stable. limited to 5V/µs by the short-circuit current. Coaxial cable can be driven directly, but for best pulse fidelity a resistor
Power Dissipation
of value equal to the characteristic impedance of the cable The LT1361/LT1362 combine high speed and large output (i.e., 75Ω) should be placed in series with the output. The drive in small packages. Because of the wide supply other end of the cable should be terminated with the same voltage range, it is possible to exceed the maximum value resistor to ground. junction temperature under certain conditions. Maximum junction temperature (T
Circuit Operation
J) is calculated from the ambient temperature (TA) and power dissipation (PD) as follows: The LT1361/LT1362 circuit topology is a true voltage LT1361CN8: T feedback amplifier that has the slewing behavior of a J = TA + (PD x 130°C/W) LT1361CS8: T current feedback amplifier. The operation of the circuit can J = TA + (PD x 190°C/W) LT1362CN: T be understood by referring to the simplified schematic. J = TA + (PD x 110°C/W) LT1362CS: T The inputs are buffered by complementary NPN and PNP J = TA + (PD x 150°C/W) emitter followers which drive a 500Ω resistor. The input Worst case power dissipation occurs at the maximum voltage appears across the resistor generating currents supply current and when the output voltage is at 1/2 of which are mirrored into the high impedance node. Comple- either supply voltage (or the maximum swing if less than mentary followers form an output stage which buffers the 1/2 supply voltage). For each amplifier PDMAX is: gain node from the load. The bandwidth is set by the input resistor and the capacitance on the high impedance node. PDMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL The slew rate is determined by the current available to charge the gain node capacitance. This current is the Example: LT1362 in S16 at 70°C, VS = ±5V, RL = 100Ω differential input voltage divided by R1, so the slew rate is proportional to the input. Highest slew rates are therefore PDMAX = (10V)(5.6mA) + (2.5V)2/100Ω = 119mW seen in the lowest gain configurations. For example, a 10V output step in a gain of 10 has only a 1V input step, TJMAX = 70°C + (4 x 119mW)(150°C/W) = 141°C 10
U U W U APPLICATIONS INFORMATION tion with large, sustained differential inputs
. Under whereas the same output step in unity gain has a 10 times normal, closed-loop operation, an increase of power dis- greater input step. The curve of Slew Rate vs Input Level sipation is only noticeable in applications with large slewing illustrates this relationship. The LT1361/LT1362 are tested outputs and is proportional to the magnitude of the for slew rate in a gain of –2 so higher slew rates can be differential input voltage and the percent of the time that expected in gains of 1 and –1, and lower slew rates in the inputs are apart. Measure the average supply current higher gain configurations. for the application in order to calculate the power dissipa- The RC network across the output stage is bootstrapped tion. when the amplifier is driving a light or moderate load and has no effect under normal operation. When driving a
Capacitive Loading
capacitive load (or a low value resistive load) the network The LT1361/LT1362 are stable with any capacitive load. is incompletely bootstrapped and adds to the compensa- This is accomplished by sensing the load induced output tion at the high impedance node. The added capacitance pole and adding compensation at the amplifier gain node. slows down the amplifier which improves the phase As the capacitive load increases, both the bandwidth and margin by moving the unity-gain frequency away from the phase margin decrease so there will be peaking in the pole formed by the output impedance and the capacitive frequency domain and in the transient response as shown load. The zero created by the RC combination adds phase in the typical performance curves. The photo of the small to ensure that even for very large load capacitances, the signal response with 500pF load shows 60% peaking. The total phase lag can never exceed 180 degrees (zero phase large signal response shows the output slew rate being margin) and the amplifier remains stable. limited to 5V/µs by the short-circuit current. Coaxial cable can be driven directly, but for best pulse fidelity a resistor
Power Dissipation
of value equal to the characteristic impedance of the cable The LT1361/LT1362 combine high speed and large output (i.e., 75Ω) should be placed in series with the output. The drive in small packages. Because of the wide supply other end of the cable should be terminated with the same voltage range, it is possible to exceed the maximum value resistor to ground. junction temperature under certain conditions. Maximum junction temperature (T
Circuit Operation
J) is calculated from the ambient temperature (TA) and power dissipation (PD) as follows: The LT1361/LT1362 circuit topology is a true voltage LT1361CN8: T feedback amplifier that has the slewing behavior of a J = TA + (PD x 130°C/W) LT1361CS8: T current feedback amplifier. The operation of the circuit can J = TA + (PD x 190°C/W) LT1362CN: T be understood by referring to the simplified schematic. J = TA + (PD x 110°C/W) LT1362CS: T The inputs are buffered by complementary NPN and PNP J = TA + (PD x 150°C/W) emitter followers which drive a 500Ω resistor. The input Worst case power dissipation occurs at the maximum voltage appears across the resistor generating currents supply current and when the output voltage is at 1/2 of which are mirrored into the high impedance node. Comple- either supply voltage (or the maximum swing if less than mentary followers form an output stage which buffers the 1/2 supply voltage). For each amplifier PDMAX is: gain node from the load. The bandwidth is set by the input resistor and the capacitance on the high impedance node. PDMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL The slew rate is determined by the current available to charge the gain node capacitance. This current is the Example: LT1362 in S16 at 70°C, VS = ±5V, RL = 100Ω differential input voltage divided by R1, so the slew rate is proportional to the input. Highest slew rates are therefore PDMAX = (10V)(5.6mA) + (2.5V)2/100Ω = 119mW seen in the lowest gain configurations. For example, a 10V output step in a gain of 10 has only a 1V input step, TJMAX = 70°C + (4 x 119mW)(150°C/W) = 141°C 10
