Datasheet ADP5050 (Analog Devices) - 10

ADP5050 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6.
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a PVIN1 to PGND −0.3 V to +18 V stress rating only; functional operation of the product at these PVIN2 to PGND −0.3 V to +18 V or any other conditions above those indicated in the operational PVIN3 to PGND3 −0.3 V to +18 V section of this specification is not implied. Operation beyond PVIN4 to PGND4 −0.3 V to +18 V the maximum operating conditions for extended periods may PVIN5 to GND −0.3 V to +6.5 V affect product reliability. SW1 to PGND −0.3 V to +18 V
THERMAL RESISTANCE
SW2 to PGND −0.3 V to +18 V θ SW3 to PGND3 −0.3 V to +18 V JA is specified for the worst-case conditions, that is, a device SW4 to PGND4 −0.3 V to +18 V soldered in a circuit board for surface-mount packages. PGND to GND −0.3 V to +0.3 V
Table 7. Thermal Resistance
PGND3 to GND −0.3 V to +0.3 V
Package Type θJA θJC Unit
PGND4 to GND −0.3 V to +0.3 V 48-Lead LFCSP 27.87 2.99 °C/W BST1 to SW1 −0.3 V to +6.5 V BST2 to SW2 −0.3 V to +6.5 V
ESD CAUTION
BST3 to SW3 −0.3 V to +6.5 V BST4 to SW4 −0.3 V to +6.5 V DL1 to PGND −0.3 V to +6.5 V DL2 to PGND −0.3 V to +6.5 V SS12, SS34 to GND −0.3 V to +6.5 V EN1, EN2, EN3, EN4, EN5 to GND −0.3 V to +6.5 V VREG to GND −0.3 V to +6.5 V SYNC/MODE to GND −0.3 V to +6.5 V VOUT5, FB5 to GND −0.3 V to +6.5 V RT to GND −0.3 V to +3.6 V INT, PWRGD to GND −0.3 V to +6.5 V FB1, FB2, FB3, FB4 to GND1 −0.3 V to +3.6 V FB2 to GND2 −0.3 V to +6.5 V FB4 to GND2 −0.3 V to +7 V COMP1, COMP2, COMP3, COMP4 −0.3 V to +3.6 V to GND VDD, VDDIO to GND −0.3 V to +3.6 V SCL, SDA −0.3 V to VDDIO + 0.3 V Storage Temperate Range −65°C to +150°C Operational Junction Temperature −40°C to +125°C Range 1 This rating applies to the adjustable output voltage models of the ADP5050. 2 This rating applies to the fixed output voltage models of the ADP5050. Rev. C | Page 10 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE