Datasheet LTC3388-1, LTC3388-3 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 20V High Efficiency Nanopower Step-Down Regulator |
| Pages / Page | 22 / 9 — PIN FUNCTIONS. EN (Pin 1):. VOUT (Pin 6):. IN2 (Pin 7):. STBY (Pin 2):. … |
| File Format / Size | PDF / 381 Kb |
| Document Language | English |
PIN FUNCTIONS. EN (Pin 1):. VOUT (Pin 6):. IN2 (Pin 7):. STBY (Pin 2):. D1 (Pin 8):. D0 (Pin 9):. CAP (Pin 3):. PGOOD (Pin 10):
Model Line for this Datasheet
Text Version of Document
LTC3388-1/LTC3388-3
PIN FUNCTIONS EN (Pin 1):
Enable Input. Logic level input referenced to
VOUT (Pin 6):
Sense pin used to monitor the output volt- VIN2. A logic high on EN will enable the buck converter. age and adjust it through internal feedback. Driving EN to VIN2 will result in no additional quiescent
V
current on V
IN2 (Pin 7):
Internal low voltage rail to serve as gate drive IN. However, if EN is driven near VIH or VIL for buck NMOS switch. Also serves as a logic high rail for 40nA of additional quiescent current can appear on VIN. output voltage select bits D0 and D1. A 4.7µF capacitor
STBY (Pin 2):
Standby Input. Logic level input referenced should be connected from VIN2 to GND. This pin is not to VIN2. A logic high on STBY will place the part in standby intended for use as an external system rail. mode. Driving STBY to VIN2 will result in no additional
D1 (Pin 8):
Output Voltage Select Bit. D1 should be tied quiescent current on VIN. However, if STBY is driven high to V near V IN2 or low to GND to select desired VOUT (see IH or VIL 40nA of additional quiescent current can Table 1). appear on VIN.
D0 (Pin 9):
Output Voltage Select Bit. D0 should be tied
CAP (Pin 3):
Internal rail referenced to VIN to serve as gate high to V drive for buck PMOS switch. A 1µF capacitor should be IN2 or low to GND to select desired VOUT (see Table 1). connected between CAP and VIN. This pin is not intended for use as an external system rail.
PGOOD (Pin 10):
Power Good Open-Drain NMOS Output. The PGOOD pin is Hi-Z when V
V
OUT is above 92% of the
IN (Pin 4):
Input Voltage. A 2.2µF or larger capacitor target value. should be connected from VIN to GND.
GND (Exposed Pad Pin 11):
Ground. The exposed pad
SW (Pin 5):
Switch Pin for the Buck Switching Regulator. should be connected to a continuous ground plane on the A 22µH or larger inductor should be connected from SW second layer of the printed circuit board by several vias to VOUT. directly under the LTC3388-1/LTC3388-3. 338813fa For more information www.linear.com/LTC3388 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Application Related Parts
PIN FUNCTIONS EN (Pin 1):
Enable Input. Logic level input referenced to
VOUT (Pin 6):
Sense pin used to monitor the output volt- VIN2. A logic high on EN will enable the buck converter. age and adjust it through internal feedback. Driving EN to VIN2 will result in no additional quiescent
V
current on V
IN2 (Pin 7):
Internal low voltage rail to serve as gate drive IN. However, if EN is driven near VIH or VIL for buck NMOS switch. Also serves as a logic high rail for 40nA of additional quiescent current can appear on VIN. output voltage select bits D0 and D1. A 4.7µF capacitor
STBY (Pin 2):
Standby Input. Logic level input referenced should be connected from VIN2 to GND. This pin is not to VIN2. A logic high on STBY will place the part in standby intended for use as an external system rail. mode. Driving STBY to VIN2 will result in no additional
D1 (Pin 8):
Output Voltage Select Bit. D1 should be tied quiescent current on VIN. However, if STBY is driven high to V near V IN2 or low to GND to select desired VOUT (see IH or VIL 40nA of additional quiescent current can Table 1). appear on VIN.
D0 (Pin 9):
Output Voltage Select Bit. D0 should be tied
CAP (Pin 3):
Internal rail referenced to VIN to serve as gate high to V drive for buck PMOS switch. A 1µF capacitor should be IN2 or low to GND to select desired VOUT (see Table 1). connected between CAP and VIN. This pin is not intended for use as an external system rail.
PGOOD (Pin 10):
Power Good Open-Drain NMOS Output. The PGOOD pin is Hi-Z when V
V
OUT is above 92% of the
IN (Pin 4):
Input Voltage. A 2.2µF or larger capacitor target value. should be connected from VIN to GND.
GND (Exposed Pad Pin 11):
Ground. The exposed pad
SW (Pin 5):
Switch Pin for the Buck Switching Regulator. should be connected to a continuous ground plane on the A 22µH or larger inductor should be connected from SW second layer of the printed circuit board by several vias to VOUT. directly under the LTC3388-1/LTC3388-3. 338813fa For more information www.linear.com/LTC3388 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Application Related Parts
