Datasheet ADP5020 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Power Management Unit for Imaging Modules |
| Pages / Page | 28 / 7 — ADP5020. I2C TIMING SPECIFICATIONS. Table 6. Parameter Min. Max Unit. … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADP5020. I2C TIMING SPECIFICATIONS. Table 6. Parameter Min. Max Unit. Description. Timing Diagram. SDA. tBUF. FALL. LOW. tRISE. SU,DAT. tHD,STA
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ADP5020 I2C TIMING SPECIFICATIONS Table 6. Parameter Min Max Unit Description
fSCL 400 kHz SCL clock frequency tHIGH 0.6 μs SCL high time tLOW 1.3 μs SCL low time tSU,DAT 100 ns Data setup time t 1 HD,DAT 0 0.9 μs Data hold time tSU,STA 0.6 μs Setup time for repeated start tHD,STA 0.6 μs Hold time for start/repeated start tBUF 1.3 μs Bus free time between a stop condition and a start condition tSU,STO 0.6 μs Setup time for stop condition tRISE 20 + 0.1CB 300 ns Rise time of SCL/SDA t FALL 20 + 0.1CB 300 ns Fall time of SCL/SDA tSP 0 50 ns Pulse width of suppressed spike C 2 B 400 pF Capacitive load for each bus line 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the SCL falling edge. 2 CB is the total capacitance of one bus line in picofarads (pF).
Timing Diagram SDA tBUF t t t FALL LOW tRISE t FALL t SU,DAT tHD,STA SP tRISE SCL tHD,DAT tHIGH tSU,STA tSU,STO S Sr P S S = START CONDITION
03
Sr = START REPEATED CONDITION
0 4-
P = STOP CONDITION
77 07 Figure 3. I2C Interface Timing Diagram Rev. 0 | Page 7 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE
ADP5020 I2C TIMING SPECIFICATIONS Table 6. Parameter Min Max Unit Description
fSCL 400 kHz SCL clock frequency tHIGH 0.6 μs SCL high time tLOW 1.3 μs SCL low time tSU,DAT 100 ns Data setup time t 1 HD,DAT 0 0.9 μs Data hold time tSU,STA 0.6 μs Setup time for repeated start tHD,STA 0.6 μs Hold time for start/repeated start tBUF 1.3 μs Bus free time between a stop condition and a start condition tSU,STO 0.6 μs Setup time for stop condition tRISE 20 + 0.1CB 300 ns Rise time of SCL/SDA t FALL 20 + 0.1CB 300 ns Fall time of SCL/SDA tSP 0 50 ns Pulse width of suppressed spike C 2 B 400 pF Capacitive load for each bus line 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the SCL falling edge. 2 CB is the total capacitance of one bus line in picofarads (pF).
Timing Diagram SDA tBUF t t t FALL LOW tRISE t FALL t SU,DAT tHD,STA SP tRISE SCL tHD,DAT tHIGH tSU,STA tSU,STO S Sr P S S = START CONDITION
03
Sr = START REPEATED CONDITION
0 4-
P = STOP CONDITION
77 07 Figure 3. I2C Interface Timing Diagram Rev. 0 | Page 7 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE
