Datasheet ADP5020 (Analog Devices) - 8

ADP5020 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7.
θ
Parameter Rating
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. VDD1, VDD2, VDD3 −0.3 V to +6 V SW1, SW2 −0.3 V to +6 V
Table 8. Thermal Resistance
VOUT1, VOUT2, VOUT3 −0.3 V to +6 V
Package Type θJA θJC Unit
VDD_IO −0.3V to +3.6 V 20-Lead LFCSP (CP-20-4) 47.4 4.3 °C/W EN, SCL, SDA, SYNC, XSHTDN −0.3 V to VDD_IO + 0.3 V Operating Temperature Range
Thermal Data
Ambient −40°C to +85°C Junction-to-ambient thermal resistance (θJA) of the package is Junction −40°C to +125°C based on modeling and calculation using a 4-layer board. The Storage Temperature Range −65°C to +150°C junction-to-ambient thermal resistance is highly dependent on Lead Temperature 260°C the application and board layout. In applications where high maxi- Soldering (10 sec) 260°C mum power dissipation exists, attention to thermal board design Vapor Phase (60 sec) 215°C is required. The value of θJA may vary, depending on PCB material, Infrared (15 sec) 220°C layout, and environmental conditions. The specified value of θJA VESD is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board, as per Machine Model Range −200 V to +200 V JEDEC standards. For more information, see the AN-772 Human Body Model Range −2000 V to +2000 V Application Note, A Design and Manufacturing Guide for the Charged Device Model ±750 V Lead Frame Chip Scale Package (LFCSP). Stresses above those listed under Absolute Maximum Ratings
ESD CAUTION
may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The ADP5020 can be damaged when the junction temperature (TJ) limits are exceeded. Monitoring the ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications having moderate power dis- sipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The TJ of the device is dependent on the ambient temperature (TA), the power dissipation (PD) of the device, and the junction-to-ambient thermal resistance of the package (θJA). Maximum TJ is calculated from TA and PD using the following formula: TJ = TA + (PD × θJA) Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE