Datasheet MCP6V51 (Microchip) - 5

link to page 7 link to page 7 link to page 5 link to page 24 link to page 3 link to page 12 link to page 17
MCP6V51 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to
Figure 1-4
and
Figure 1-5
).
Parameters Sym. Min. Typ. Max. Units Conditions
Maximum Output Voltage Swing VOH VDD - 150 VDD - 100 — mV RL = 1 kΩ, VDD = 4.5V VDD - 2500 VDD - 1500 — RL = 1 kΩ, VDD = 45V VDD - 20 VDD - 12 — RL = 10 kΩ, VDD = 4.5V VDD - 200 VDD - 100 — RL = 10 kΩ, VDD = 45V Output Short Circuit Current ISC+ — 46 — mA ISC- — 36 — mA Closed-loop Output Resistance ROUT — 16 — Ω f = 0.1 MHz, IO = 0, G = 1 Capacitive Load Drive CL — 100 — pF G = 1
Power Supply
Supply Voltage VDD 4.5 — 45 V Quiescent Current per Amplifier IQ 310 460 590 µA VDD = 4.5V, IO = 0 310 470 590 µA VDD = 45V, IO = 0 — 540 670 µA IO = 0, TA = -40 to +125°C
(Note 1) (Figure 2-22 )
Power-on Reset (POR) Trip VPOR — 2.3 — V Voltage
Note 1:
Not production tested. Limits set by characterization and/or simulation and provided as design guidance only.
2: Figure 2-17
shows how VCML and VCMH changed across temperature for the first production lot.
AC ELECTRICAL SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to
Figure 1-4
and
Figure 1-5
).
Parameters Sym. Min. Typ. Max. Units Conditions Amplifier AC Response
Gain Bandwidth Product GBWP — 1.8 — MHz VDD = 4.5V, VIN = 10 mVpp, Gain = 100 — 2 — MHz VDD = 45V, VIN = 10 mVpp, Gain = 100 Slew Rate SR — 1.2 — V/µs
(Figure 2-44)
Phase Margin PM — 66 — deg. VDD = 45V
Amplifier Noise Response
Input Noise Voltage Eni — 0.1 — µVP-P f = 0.01 Hz to 1 Hz Eni — 0.21 — µVP-P f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 10.2 — nV/√Hz f = 1 kHz Input Noise Current Density ini — 4 — fA/√Hz
Amplifier Step Response
Start-Up Time tSTR — 200 — µs G = +1, 1% VOUT settling
(Note 1)
Offset Correction Settling Time tSTL — 45 — µs G = +1, VIN step of 2V, VOS within ±100 µV of its final value
Note 1:
Behavior may vary with different gains; see
Section 4.3.3 “Offset at Power-Up”
.
2:
tSTL and tODR include some uncertainty due to clock edge timing.  2018 Microchip Technology Inc. DS20006136A-page 5 Document Outline 45V, 2 MHz Zero-Drift Op Amp with EMI Filtering Features Typical Applications Design Aids Related Parts General Description Package Types Typical Application Circuit FIGURE 1: Input Offset Voltage vs. Ambient Temperature with VDD = 4.5V. FIGURE 2: Input Offset Voltage vs. Ambient Temperature with VDD = 45V. 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Electrical Specifications DC Electrical Specifications AC Electrical Specifications Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start-Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. 1.4 Test Circuits FIGURE 1-4: AC and DC Test Circuit for Most Noninverting Gain Conditions. FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-6: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-4: Input Offset Voltage vs. Output Voltage with VDD = 4.5V. FIGURE 2-5: Input Offset Voltage vs. Output Voltage with VDD = 45V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Voltage with VDD = 4.5V FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 45V. FIGURE 2-8: CMRR. FIGURE 2-9: PSRR. FIGURE 2-10: DC Open-Loop Gain. FIGURE 2-11: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-12: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-15: Input Bias and Offset Currents vs. Ambient Temperature with VDD = 45V. FIGURE 2-16: Input Bias Current vs. Input Voltage (Below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-17: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-18: Output Voltage Headroom vs. Output Current. FIGURE 2-19: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-20: Output Voltage Headroom vs Temperature RL = 10 kΩ. FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-22: Supply Current vs. Power Supply Voltage. 2.3 Frequency Response FIGURE 2-23: CMRR and PSRR vs. Frequency. FIGURE 2-24: Open-Loop Gain vs. Frequency with VDD = 4.5V. FIGURE 2-25: Open-Loop Gain vs. Frequency with VDD = 45V. FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-28: Closed-Loop Output Impedance vs. Frequency with VDD = 4.5V. FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency with VDD = 45V. FIGURE 2-30: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-31: EMIRR vs. Frequency. 2.4 Input Noise FIGURE 2-32: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. FIGURE 2-33: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 4.5V. FIGURE 2-34: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 45V. 2.5 Time Response FIGURE 2-35: Input Offset Voltage vs. Time with Temperature Change. FIGURE 2-36: Input Offset Voltage vs. Time at Power-Up. FIGURE 2-37: The MCP6V51 Shows No Input Phase Reversal with Overdrive. FIGURE 2-38: Noninverting Small Signal Step Response. FIGURE 2-39: Noninverting Large Signal Step Response. FIGURE 2-40: Noninverting 40 VPP Step Response. FIGURE 2-41: Inverting Small Signal Step Response. FIGURE 2-42: Inverting Large Signal Step Response. FIGURE 2-43: Inverting 40 VPP Step Response. FIGURE 2-44: Slew Rate vs. Ambient Temperature. FIGURE 2-45: Output Overdrive Recovery vs. Time with G = -10 V/V. FIGURE 2-46: Output Overdrive Recovery Time vs. Inverting Gain. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Output 3.2 Analog Inputs 3.3 Power Supply Pins 4.0 Applications 4.1 Overview of Zero-Drift Operation FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs against High Voltages. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. EQUATION 4-1: EQUATION 4-2: 4.3 Application Tips EQUATION 4-3: FIGURE 4-7: Recommended RISO Values for Capacitive Loads. FIGURE 4-8: Output Resistor, RISO, Stabilizes Capacitive Loads FIGURE 4-9: Amplifier with Parasitic Capacitance. EQUATION 4-4: 4.4 Typical Applications FIGURE 4-10: Low-Side Current Sense for 1.5A Max Load Current. FIGURE 4-11: Simple Design. FIGURE 4-12: Higher Performance Design. FIGURE 4-13: RTD Sensor. 5.0 Design Aids 5.1 Microchip Advanced Part Selector (MAPS) 5.2 Analog Demonstration and Evaluation Boards 5.3 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Revision A (December 2018) Product Identification System Trademarks Worldwide Sales and Service