Datasheet ADSP-SC582, ADSP-SC583, ADSP-SC584, ADSP-SC587, ADSP-SC589, ADSP-21583, ADSP-21584, ADSP-21587 (Analog Devices) - 19

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ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587 Watchdog Timer (WDT)
• Single external reference with analog inputs between Two on-chip software watchdog timers (WDT) can be used by 0 V and 3.3 V. the Arm Cortex-A5 and/or SHARC+ cores. A software watch- • Selectable ADC clock frequency including the ability to dog can improve system availability by forcing the processors to program a prescaler. a known state, via a general-purpose interrupt, or a fault, if the • Adaptable conversion type; allows single or continuous timer expires before being reset by software. conversion with option of autoscan. The programmer initializes the count value of the timer, enables • Autosequencing capability with up to 15 autoconversions the appropriate interrupt, then enables the timer. Thereafter, in a single session. Each conversion can be programmed to the software must reload the counter before it counts down to select 1 to 15 input channels. zero from the programmed value, protecting the system from remaining in an unknown state where software that normally • 16 data registers (individually addressable) to store conver- resets the timer stops running due to an external noise condi- sion values. tion or software error.
USB 2.0 On the Go (OTG) Dual-Role Device Controller General-Purpose Counters (CNT)
There are two USB modules + PHY. USB0 supports HS/FS/LS A 32-bit counter (CNT) is provided that can operate in general- USB 2.0 on the go (OTG) and USB1 supports HS/FS USB 2.0 purpose up/down count modes and can sense 2-bit quadrature only and can be programmed to be a host or device. or binary codes as typically emitted by industrial drives or man- The USB 2.0 OTG dual-role device controller provides a low ual thumbwheels. Count direction is either controlled by a level- cost connectivity solution in industrial applications, as well as sensitive input pin or by two edge detectors. consumer mobile devices such as cell phones, digital still cam- A third counter input can provide flexible zero marker support eras, and MP3 players. The USB 2.0 controller allows these and can input the push button signal of thumbwheel devices. All devices to transfer data using a point to point USB connection three CNT0 pins have a programmable debouncing circuit. without the need for a PC host. The module can operate in a tra- ditional USB peripheral only mode as well as the host mode Internal signals forwarded to a GP timer enable this timer to presented in the OTG supplement to the USB 2.0 specification. measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by inter- The USB clock is provided through a dedicated external crystal rupts when programmed count values are exceeded. or crystal oscillator. The USB OTG dual-role device controller includes a PLL with
PCI Express (PCIe)
programmable multipliers to generate the necessary internal A PCI express interface (PCIe) is available on some product clocking frequency for the USB. variants (see Table 2 and Table 3). This single, bidirectional lane can be configured to be either a root complex (RC) or end point
Media Local Bus (Media LB)
(EP) system. The PCIe interface has the following features: The automotive model has a Media LB (MLB) slave interface • Designed to be compliant with the PCI Express Base that allows the processors to function as a media local bus Specification 3.0 device. It includes support for both 3-pin and 6-pin media local bus protocols. The MLB 3-pin configuration supports speeds up • Support for transfers at either 2.5 Gbps (Gen 1) or 5.0 Gbps to 1024 × FS. The MLB 6-pin configuration supports a speed of (Gen 2) in each direction 2048 × FS. The MLB also supports up to 64 logical channels • Support for 8b/10b encode and decode with up to 468 bytes of data per MLB frame. • Lane reversal and lane polarity inversion The MLB interface supports MOST25, MOST50, and MOST150 • Flow control of data in both the transmit and receive data rates and operates in slave mode only. directions
2-Wire Controller Interface (TWI)
• Support for removal of corrupted packets for error detec- The processors include three 2-wire interface (TWI) modules tion and recovery that provide a simple exchange method of control data between • Maximum transaction payload of 256 bytes multiple devices. The TWI module is compatible with the widely used I2C bus standard. The TWI module offers the
Housekeeping Analog-to-Digital Converter (HADC)
capabilities of simultaneous master and slave operation and The housekeeping analog-to-digital converter (HADC) pro- support for both 7-bit addressing and multimedia data arbitra- vides a general-purpose, multichannel successive tion. The TWI interface utilizes two pins for transferring clock approximation ADC. It supports the following set of features: (TWI_SCL) and data (TWI_SDA) and supports the protocol at speeds up to 400 kb/sec. The TWI interface pins are compatible • 12-bit ADC core with built in sample-and-hold. with 5 V logic levels. • 8 single-ended input channels that can be extended to 15 Additionally, the TWI module is fully compatible with serial channels by adding an external channel multiplexer. camera control bus (SCCB) functionality for easier control of • Throughput rates up to 1 MSPS. various CMOS camera sensor devices. Rev. B | Page 19 of 173 | December 2018 Document Outline System Features Memory Additional Features Table of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC58x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC58x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers (USTAT) Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict-Cache Branch Target Buffer/Branch Predictor Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant C ode (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Arm TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Ports (LP) ADC Control Module (ACM) Interface 3-Phase Pulse Width Modulator (PWM) Units Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support (10/100/1000 EMAC Only) Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) PCI Express (PCIe) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller Media Local Bus (Media LB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration FFT/IFFT Accelerator Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator Harmonic Analysis Engine (HAE) Sinus Cardinalis (SINC) Filter Digital Transmission Content Protection (DTCP) System Design Clock Management Reset Control Unit (RCU) Real-Time Clock (RTC) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 349-Ball CSP_BGA Package 529-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 529-Ball CSP_BGA Package ADSP-SC58x/ADSP-2158x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LP) Serial Ports (SPORT) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port SPI Port—Master Timing SPI Port—Slave Timing SPI Port—SPI Ready (SPIx_RDY) Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose I/O Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing PWM — Medium Precision (MP) Mode Timing PWM — Heightened Precision (HP) Mode Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) PCI Express (PCIe) 10/100 EMAC Timing (ETH0 and ETH1) 10/100/1000 EMAC Timing (ETH0 Only) Sinus Cardinalis (SINC) Filter Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode Media LB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 349-Ball CSP_BGA ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 529-Ball CSP_BGA Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide