Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 8

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ADSP-21467/ ADSP-21469
Note that the external memory bank addresses shown are for
Digital Applications Interface (DAI)
normal-word (32-bit) accesses. If 48-bit instructions, as well as The digital applications interface (DAI) provides the ability to 32-bit data, are both placed in the same external memory bank, connect various peripherals to any of the DAI pins care must be taken while mapping them to avoid overlap. (DAI_P20–1).
Asynchronous Memory Controller
Programs make these connections using the signal routing unit The asynchronous memory controller provides a configurable (SRU), shown in Figure 1 on Page 1. interface for up to four separate banks of memory or I/O The SRU is a matrix routing unit (or group of multiplexers) that devices. Each bank can be independently programmed with dif- enables the peripherals provided by the DAI to be intercon- ferent timing parameters, enabling connection to a wide variety nected under software control. This allows easy use of the DAI of memory devices including SRAM, Flash, and EPROM, as well associated peripherals for a much wider variety of applications as I/O devices that interface with standard memory control by using a larger set of algorithms than is possible with noncon- lines. Bank 0 occupies a 2M word window and banks 1, 2, and 3 figurable signal paths. occupy a 4M word window in the processor’s address space but, The DAI includes the peripherals described in the following if not fully populated, these windows are not made contiguous sections. by the memory controller logic.
Serial Ports External Port Throughput
The processors feature eight synchronous serial ports that pro- The throughput for the external port, based on a 400 MHz vide an inexpensive interface to a wide variety of digital and clock, is 66M bytes/s for the AMI and 800M bytes/s for DDR2. mixed-signal peripheral devices such as Analog Devices’
Link Ports
AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The Two 8-bit wide link ports can connect to the link ports of other data lines can be programmed to either transmit or receive and DSPs or peripherals. Link ports are bidirectional ports having each data line has a dedicated DMA channel. eight data lines, an acknowledge line, and a clock line. Link ports can operate at a maximum frequency of 166 MHz. Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or
MediaLB
four full duplex TDM streams of 128 channels per frame. The automotive model has a MLB interface which allows the The serial ports operate at a maximum data rate of fPCLK/4. processors to function as a media local bus device. It includes Serial port data can be automatically transferred to and from support for both 3-pin and 5-pin media local bus protocols. It on-chip memory/external memory via dedicated DMA chan- supports speeds up to 1024 FS (49.25M bits/sec, FS = 48.1 kHz) nels. Each of the serial ports can work in conjunction with and up to 31 logical channels, with up to 124 bytes of data per another serial port to provide TDM support. One SPORT pro- media local bus frame. vides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. The MLB interface supports MOST25 and MOST50 data rates. The isochronous mode of transfer is not supported. Serial ports operate in five modes:
Pulse-Width Modulation
• Standard DSP serial mode • Multichanne l (TDM) mode The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required • I2S mode switching patterns for various applications related to motor and • Packed I2S mode engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM • Left-justified mode waveforms. In addition, it can generate complementary signals
S/PDIF-Compatible Digital Audio Receiver/Transmitter
on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four PWM The S/PDIF receiver/transmitter has no separate DMA chan- waveforms). The PWM generator is capable of operating in two nels. It receives audio data in serial format and converts it into a distinct modes while generating center-aligned PWM wave- biphase encoded signal. The serial data input to the receiver/ forms: single update mode or double update mode. transmitter can be formatted as left justified, I2S or right justi- fied with word widths of 16, 18, 20, or 24 bits. The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in The serial data, clock, and frame sync inputs to the S/PDIF total. Each PWM group produces two pairs of PWM signals on receiver/transmitter are routed through the signal routing unit the four PWM outputs. (SRU). They can come from a variety of sources, such as the SPORTs, external pins, and the precision clock generators (PCGs), and are controlled by the SRU control registers. Rev. B | Page 8 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide