Datasheet UT69RH051 (Aeroflex) - 3
| Manufacturer | Aeroflex |
| Description | Radiation-Hardened MicroController |
| Pages / Page | 20 / 3 — RST:. 2.1 Hardware/Software Interface. 2.1.1 Memory. ALE:. PSEN:. EA:. … |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
RST:. 2.1 Hardware/Software Interface. 2.1.1 Memory. ALE:. PSEN:. EA:. XTAL1:. XTAL2:. 2.1.2 Special Function Registers
Model Line for this Datasheet
- 5962F9563801QQA 5962F9563801QQC 5962F9563801QQX 5962F9563801QYA 5962F9563801QYC 5962F9563801QYX 5962F9563801VQA 5962F9563801VQC 5962F9563801VQX 5962F9563801VYA 5962F9563801VYC 5962F9563801VYX 5962G9563801QQA 5962G9563801QQC 5962G9563801QQX 5962G9563801QYA 5962G9563801QYC 5962G9563801QYX 5962G9563801VQA 5962G9563801VQC 5962G9563801VQX 5962G9563801VYA 5962G9563801VYC 5962G9563801VYX 5962H9563801QQA 5962H9563801QQC 5962H9563801QQX 5962H9563801QYA 5962H9563801QYC 5962H9563801QYX 5962H9563801VQA 5962H9563801VQC 5962H9563801VQX 5962H9563801VYA 5962H9563801VYC 5962H9563801VYX 5962R9563801QQA 5962R9563801QQC 5962R9563801QQX 5962R9563801QYA 5962R9563801QYC 5962R9563801QYX 5962R9563801VQA 5962R9563801VQC 5962R9563801VQX 5962R9563801VYA 5962R9563801VYC 5962R9563801VYX UT69RH051P-CA UT69RH051P-CC UT69RH051P-CX UT69RH051W-PA UT69RH051W-PC UT69RH051W-PX
Text Version of Document
RST:
Reset Input. A high on this input for 24 oscillator periods
2.1 Hardware/Software Interface
while the oscillator is running resets the device. All ports and SFRs reset to their default conditions. Internal data memory is
2.1.1 Memory
undefined after reset. Program execution begins within 12 The UT69RH051 has a separate address space for Program and oscillator periods (one machine cycle) after the RST signal is Data Memory. Internally, the UT69RH051 contains 256 bytes of brought low. RST contains an internal pulldown resistor to allow Data Memory. It addresses up to 64Kbytes of external Data implementing power-up reset with only an external capacitor. Memory and 64Kbytes of external Program Memory.
ALE:
Address Latch Enable. The ALE output is a pulse for 2.1.1.1 Program Memory latching the low byte of the address during accesses to external There is no internal program memory in the UT69RH051. All memory. In normal operation, the ALE pulse is output every sixth program memory is accessed as external through ports P0 and oscillator cycle and may be used for external timing or clocking. P2. The EA pin must be tied to VSS (ground) to enable access to However, during each access to external Data Memory (MOVX external locations 0000H through 7FFFH. Following reset, the instruction), one ALE pulse is skipped. UT69RH051 fetches the first instruction at address 0000h.
PSEN:
Program Store Enable. This active low signal is the read 2.1.1.2 Data Memory strobe to the external program memory. PSEN activates every The UT69RH051 implements 256 bytes of internal data RAM. sixth oscillator cycle except that two PSEN activations are The upper 128 bytes of this RAM occupy a parallel address space skipped during external data memory accesses. to the SFRs. The CPU determines if the internal access to an address above 7F
EA:
External Access Enable. This pin should be strapped to V H is to the upper 128 bytes of RAM or to the SS SFR space by the addressing mode of the instruction. If direct (Ground) for the UT69RH051. addressing is used, the access is to the SFR space. If indirect
XTAL1:
Input to the inverting oscillator amplifier. addressing is used, the access is to the internal RAM. Stack operations are indirectly addressed so the upper portion of RAM
XTAL2:
Output from the inverting oscillator amplifier. can be used as stack space. Figure 3 shows the organization of the internal Data Memory. The first 32 bytes are reserved for four register banks of eight bytes each. The processor uses one of the four banks as its working registers depending on the RS1 and RS0 bits in the PSW SFR. At reset, bank 0 is selected. If four register banks are not required, use the unused banks as general purpose scratch pad memory. The next 16 bytes (128 bits) are individually bit addressable. The remaining bytes are byte addressable and can be used as general purpose scratch pad memory. For addresses 0 - 7FH, use either direct or indirect addressing. For addresses larger than 7FH, use only indirect addressing. In addition to the internal Data Memory, the processor can access 64Kbytes of external Data Memory. The MOVX instruction accesses external Data Memory.
2.1.2 Special Function Registers
Table 3 contains the SFR memory map. Unoccupied addresses are not implemented on the device. Read accesses to these addresses will return unknown values and write accesses will have no effect. 3
Reset Input. A high on this input for 24 oscillator periods
2.1 Hardware/Software Interface
while the oscillator is running resets the device. All ports and SFRs reset to their default conditions. Internal data memory is
2.1.1 Memory
undefined after reset. Program execution begins within 12 The UT69RH051 has a separate address space for Program and oscillator periods (one machine cycle) after the RST signal is Data Memory. Internally, the UT69RH051 contains 256 bytes of brought low. RST contains an internal pulldown resistor to allow Data Memory. It addresses up to 64Kbytes of external Data implementing power-up reset with only an external capacitor. Memory and 64Kbytes of external Program Memory.
ALE:
Address Latch Enable. The ALE output is a pulse for 2.1.1.1 Program Memory latching the low byte of the address during accesses to external There is no internal program memory in the UT69RH051. All memory. In normal operation, the ALE pulse is output every sixth program memory is accessed as external through ports P0 and oscillator cycle and may be used for external timing or clocking. P2. The EA pin must be tied to VSS (ground) to enable access to However, during each access to external Data Memory (MOVX external locations 0000H through 7FFFH. Following reset, the instruction), one ALE pulse is skipped. UT69RH051 fetches the first instruction at address 0000h.
PSEN:
Program Store Enable. This active low signal is the read 2.1.1.2 Data Memory strobe to the external program memory. PSEN activates every The UT69RH051 implements 256 bytes of internal data RAM. sixth oscillator cycle except that two PSEN activations are The upper 128 bytes of this RAM occupy a parallel address space skipped during external data memory accesses. to the SFRs. The CPU determines if the internal access to an address above 7F
EA:
External Access Enable. This pin should be strapped to V H is to the upper 128 bytes of RAM or to the SS SFR space by the addressing mode of the instruction. If direct (Ground) for the UT69RH051. addressing is used, the access is to the SFR space. If indirect
XTAL1:
Input to the inverting oscillator amplifier. addressing is used, the access is to the internal RAM. Stack operations are indirectly addressed so the upper portion of RAM
XTAL2:
Output from the inverting oscillator amplifier. can be used as stack space. Figure 3 shows the organization of the internal Data Memory. The first 32 bytes are reserved for four register banks of eight bytes each. The processor uses one of the four banks as its working registers depending on the RS1 and RS0 bits in the PSW SFR. At reset, bank 0 is selected. If four register banks are not required, use the unused banks as general purpose scratch pad memory. The next 16 bytes (128 bits) are individually bit addressable. The remaining bytes are byte addressable and can be used as general purpose scratch pad memory. For addresses 0 - 7FH, use either direct or indirect addressing. For addresses larger than 7FH, use only indirect addressing. In addition to the internal Data Memory, the processor can access 64Kbytes of external Data Memory. The MOVX instruction accesses external Data Memory.
2.1.2 Special Function Registers
Table 3 contains the SFR memory map. Unoccupied addresses are not implemented on the device. Read accesses to these addresses will return unknown values and write accesses will have no effect. 3
