Datasheet ADUM6132 (Analog Devices) - 10

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ADuM6132 Data Sheet TERMINOLOGY Channel-to-Channel Matching Minimum Pulse Width
Channel-to-channel matching with rising or falling matching The minimum pulse width is the shortest pulse width at which edge polarity is the magnitude of the propagation delay differ- the specified pulse width distortion is guaranteed. Operation ence between two channels of the same part when the inputs below the minimum pulse width is not recommended. are both rising edges or both falling edges. The loads on each
Part-to-Part Matching
channel are equal. Part-to-part matching is the magnitude of the propagation Channel-to-channel matching with rising vs. falling opposite delay difference between the same channels of two different edge polarity is the magnitude of the propagation delay differ- parts. This includes rising vs. rising edges, falling vs. falling ence between two channels of the same part when one input is edges, or rising vs. falling edges. The supply voltages, temp- a rising edge and one input is a falling edge. The loads on each eratures, and loads of each part are equal. channel are equal.
Propagation Delay Maximum Output Current
The propagation delay is the time that it takes a logic signal to The maximum output current is the maximum isolated supply propagate through a component. The propagation delay to a current that the ADuM6132 can provide. This current supports logic low output may differ from the propagation delay to a external loads as well as the needs of the ADuM6132 Channel A logic high output. output circuitry. This is achieved via external connection of the The tPHL propagation delay is measured from the 50% level VISO pin to the VDDA pin and of the GNDISO pin to the GNDA pin of the falling edge of the VIA or VIB signal to the 50% level of (see Figure 16). The net current available to power external loads the falling edge of the VOA or VOB signal. The tPLH propagation is the ADuM6132 output current, IISO, minus the Channel A delay is measured from the 50% level of the rising edge of the supply current, IDDA. VIA or VIB signal to the 50% level of the rising edge of the VOA
Maximum Switching Frequency
or VOB signal. The maximum switching frequency is the maximum signal
Capacitive Load (CL)
frequency at which the specified timing parameters are guar- The output capacitive load simulates a typical FET, IGBT, or anteed. Operation beyond the maximum switching frequency buffer for timing or current measurements. This load includes is not recommended, because high switching rates can cause all discrete and parasitic capacitive loads on the output. droop in the output supply voltage. Rev. B | Page 10 of 16 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Electrical Characteristics Package Characteristics Regulatory Information Insulation and Safety-Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Recommended Operation Conditions Absolute Maximum Values ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Applications Information Typical Application Usage PCB Layout Thermal Analysis Undervoltage Lockout Propagation Delay-Related Parameters Magnetic Field Immunity Insulation Lifetime Outline Dimensions Ordering Guide