Datasheet ADHV4702-1 (Analog Devices) - 15

link to page 3 link to page 15 link to page 15 link to page 15 link to page 19 link to page 19 link to page 15 link to page 16 link to page 16
Data Sheet ADHV4702-1 THEORY OF OPERATION
The ADHV4702-1 is a high voltage (220 V) precision amplifier
SLEW BOOST CIRCUIT AND PROTECTION
designed using the next generation of proprietary bipolar/ The ADHV4702-1 uses a supplementary slew boosting circuit complementary metal-oxide semiconductor (CMOS)/laterally to achieve its typical slew rate of 74 V/µs across a 200 V p-p diffused metal-oxide semiconductor (BCDMOS) process from output range at unity gain. This slew boosting circuit works by Analog Devices. Figure 3 shows the functional block diagram. sensing the differential input voltage of the amplifier and The input stage architecture offers the advantages of high input converting this voltage into a dynamic current to help drive impedance with low input bias current, low input offset voltage, capacitances within the signal path of the amplifier. With low drift, and low noise for precision demanding applications, greater input voltage across the inputs, more dynamic current is such as automated test equipment (ATE). produced, which enables the amplifier to slew faster. The
INTERNAL ELECTROSTATIC DISCHARGE (ESD)
current produced by the slew boosting circuit transmits to all
PROTECTION
stages of the amplifier during slewing. As shown in Figure 43, the ADHV4702-1 has an internal ESD Internally, the ADHV4702-1 contains differential input voltage configuration to prevent damage due to overvoltage. The ESD clamps that limit transient differential signals to 4 VF, placing an protection circuitry involves current steering diodes connected upper limit on the slew boost. Large differential input voltages from the input and output pins to the power supply rails. The (which can be occur with signal frequencies approaching the ADHV4702-1 also includes internal input clamping diodes across ful power bandwidth) trigger the slew boosting circuit, the inverting and noninverting inputs to prevent large differential resulting in an increased dynamic supply current. The input voltages from damaging the input stage transistors. This relationship between slew rate and full power bandwidth (fM) is input clamping circuit greatly reduces the input impedance for given in the following equation: differential input voltages greater than the forward-biased SR = VO × 2πfM voltage (VF) of four diodes. where VO is the peak output voltage. The ESD protection circuitry remains inactive under normal operation. To avoid forward biasing the ESD diodes, do not When operating continuously at or near ful power bandwidth, overdrive the pin voltages above the absolute maximum ratings, the increased supply current may cause an increase in TJ and ensure that the input differential voltage does not exceed beyond the safe operating temperature, resulting in device 4 V damage. The dynamic safe operating area (SOA) for the EVAL- F. Additional external input clamping diodes may be required to protect the slew boost circuit. See the Slew Boost ADHV4702-1CPZ evaluation board is shown in Figure 59 in Circuit and Protection section. the Safe Operating Area section. The dynamic SOA shows the connection between the output swing and the maximum
IN– COMP DGND 12 11 10
input/output frequency for pulse response. To expand the SOA
~5V 125Ω
curve, use additional thermal management or limit the
RESERVED 9 RADJ 1
differential voltage across the inputs to 2 VF with external
~5V VEE VCC
diodes, which limits the current produced by the slew boosting
DGND
circuit and reduces the internal power dissipation. Clamping
DGND
the differential input voltage of the ADHV4702-1 in this way
125Ω IN+ 2
protects the amplifier in dynamic operation but limits slew rate
8 SD ~5V
and large signal bandwidth. Figure 44 shows a simplified
DGND
schematic with external input clamping diodes, and Figure 45 to Figure 48 show the large signal pulse response at various
7 VCC
temperatures and gains while the ADHV4702-1 inputs are
RESERVED 3 ~5V
clamped by two ON Semiconductor SBAV199LT1G diode pairs
DGND 225V ESD
at 2 VF.
5kΩ 100kΩ ~5V DGND ADHV4702-1
032
4 5 6 EXTERNAL VEE TMP OUT
16047-
INPUT VOUT CLAMPING
Figure 43. Simplified ESD Configuration
DIODES 10kΩ VIN
133 16047- Figure 44. External Input Clamping Diodes Schematic Rev. A | Page 15 of 21 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ±12 V TO ±110 V SUPPLY ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INTERNAL ELECTROSTATIC DISCHARGE (ESD) PROTECTION SLEW BOOST CIRCUIT AND PROTECTION DIGITAL GROUND (DGND) RESISTOR ADJUSTABLE QUIESCENT CURRENT (RADJ) SHUTDOWN PIN (SDB) TEMPERATURE MONITOR (TMP) OVERTEMPERATURE PROTECTION OUTPUT CURRENT DRIVE AND SHORT-CIRCUIT PROTECTION EXTERNAL COMPENSATION AND CAPACITIVE LOAD (CLOAD) DRIVING SAFE OPERATING AREA LFCSP PACKAGE AND HIGH VOLTAGE PIN SPACING EXPOSED PAD (EPAD) APPLICATIONS INFORMATION POWER SUPPLY AND DECOUPLING HIGH VOLTAGE GUARD RING HIGH VOLTAGE DAC VOLTAGE SUBTRACTOR HIGH CURRENT OUTPUT DRIVER SIGNAL RANGE EXTENDER OUTLINE DIMENSIONS ORDERING GUIDE