Datasheet AD9670 (Analog Devices) - 39

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Data Sheet AD9670 SERIAL PORT INTERFACE (SPI)
The AD9670 serial port interface allows the user to configure the only pins required for communication. Although the device is the signal chain for specific functions or operations through a synchronized during power-up, caution must be exercised when structured register space provided inside the chip. The SPI using this mode to ensure that the serial port remains synchronized offers the user added flexibility and customization, depending with the CSB line. When operating in 2-wire mode, it is recom- on the application. Addresses are accessed via the serial port mended that a 1-, 2-, or 3-byte transfer be used exclusively. Without and can be written to or read from via the port. Memory is an active CSB line, streaming mode can be entered but not exited. organized into bytes that can be further divided into fields, as In addition to word length, the instruction phase determines documented in the Memory Map section. For detailed whether the serial frame is a read or write operation, allowing operational information, see the AN-877 Application Note, the serial port to be used both to program the chip and to read Interfacing to High Speed ADCs via SPI. the contents of the on-chip memory. If the instruction is a read- Three pins define the serial port interface, or SPI: SCLK, SDIO, back operation, performing a readback causes the serial data and CSB (see Table 24). The SCLK (serial clock) pin synchro- input/output (SDIO) pin to change direction from an input to nizes the read and write data presented to the device. The SDIO an output at the appropriate point in the serial frame. (serial data input/output) pin is a dual-purpose pin that allows Data can be sent in MSB first mode or LSB first mode. MSB data to be sent to and read from the internal memory map registers first mode is the default at power-up and can be changed by of the device. The CSB (chip select bar) pin is an active low adjusting the configuration register. For more information control that enables or disables the read and write cycles. about this and other features, see the AN-877 Application Note,
Table 24. Serial Port Pins
Interfacing to High Speed ADCs via SPI.
Pin Function HARDWARE INTERFACE
SCLK Serial clock. Serial shift clock input. SCLK synchronizes The pins described in Table 24 constitute the physical interface serial interface reads and writes. between the user programming device and the serial port of the SDIO Serial data input/output. SDIO is a dual-purpose pin AD9670. The SCLK and CSB pins function as inputs when that typically serves as an input or an output, depending on the instruction sent and the relative position in the using the SPI. The SDIO pin is bidirectional, functioning as an timing frame. input during write phases and as an output during readback. CSB Chip select bar (active low). This control gates the read If multiple SDIO pins share a common connection, ensure that and write cycles. proper VOH levels are met. Figure 53 shows the number of SDIO The falling edge of CSB, in conjunction with the rising edge of pins that can be connected together and the resulting VOH level, SCLK, determines the start of the framing sequence. During an assuming the same load for each AD9670. instruction phase, a 16-bit instruction is transmitted, followed
1.800 1.795
by one or more data bytes, which is determined by Bit Field W0
1.790
and Bit Field W1. An example of the serial timing and its defini-
1.785 1.780
tions are shown in Figure 54 and Table 25.
1.775 1.770
During normal operation, CSB signals to the device that SPI
) 1.765
commands are to be received and processed. When CSB is brought
(V 1.760
low, the device processes SCLK and SDIO to execute instructions.
OH 1.755 V 1.750
Normally, CSB remains low until the communication cycle is
1.745
complete. However, if connected to a slow device, CSB can be
1.740 1.735
brought high between bytes, allowing older microcontrollers
1.730
enough time to transfer data into shift registers. CSB can be
1.725 1.720
stalled when transferring one, two, or three bytes of data. When
1.715
1 W0 and W1 are set to 11, the device enters streaming mode and
0 10 20 30 40 50 60 70 80 90 100
-04
NUMBER OF SDIO PINS CONNECTED TOGETHER
041 continues to process data, either reading or writing, until CSB is 1 1 Figure 53. SDIO Pin Loading taken high to end the communication cycle. This allows complete memory transfers without the need for additional instructions. This interface is flexible enough to be controlled either by serial Regardless of the mode, if CSB is taken high in the middle of a PROMs or by PIC microcontrollers, which provides the user with byte transfer, the SPI state machine is reset and the device waits an alternative to a full SPI controller for programming the for a new instruction. device (see the AN-812 Application Note, Microcontroller-Based In addition to the operation modes, the SPI port can be configured Serial Port Interface (SPI®) Boot Circuit). to operate in different manners. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are Rev. A | Page 39 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE