Datasheet ADL5201 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | Wide Dynamic Range, High Speed, Digitally Controlled VGA |
| Pages / Page | 26 / 2 — ADL5201. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 1/15—Rev. B to … |
| Revision | C |
| File Format / Size | PDF / 909 Kb |
| Document Language | English |
ADL5201. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 1/15—Rev. B to Rev. C. 9/13—Rev. A to Rev. B. 12/12—Rev. 0 to Rev. A
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ADL5201 Data Sheet TABLE OF CONTENTS
Features .. 1 Logic Timing ... 16 Applications ... 1 Circuit Description... 17 Functional Block Diagram .. 1 Basic Structure .. 17 General Description ... 1 Input System ... 17 Revision History ... 2 Output Amplifier .. 17 Specifications ... 3 Gain Control ... 17 Timing Diagrams .. 4 Applications Information .. 18 Absolute Maximum Ratings .. 5 Basic Connections .. 18 ESD Caution .. 5 ADC Driving ... 18 Pin Configuration and Function Descriptions ... 6 Layout Considerations ... 20 Typical Performance Characteristics ... 7 Evaluation Board .. 21 Characterization and Test Circuits ... 14 Evaluation Board Control Software ... 21 Theory of Operation .. 15 Schematics and Artwork ... 22 Digital Interface Overview .. 15 Evaluation Board Configuration Options ... 24 Parallel Digital Interface .. 15 Outline Dimensions ... 26 Serial Peripheral Interface (SPI) ... 15 Ordering Guide .. 26 Up/Down Interface .. 15
REVISION HISTORY 1/15—Rev. B to Rev. C
Changes to Table 1 .. 4 Change to Table 3 ... 6
9/13—Rev. A to Rev. B
Changed Logic Pins Absolute Maximum Rating from 3.6 V to −0.3 V to +3.6 V (not to exceed |VPOS − 0.5 V| at any time) .. 5
12/12—Rev. 0 to Rev. A
Changes to Layout Consideration Section .. 20 Updated Outline Dimensions ... 26
10/11—Revision 0: Initial Version
Rev. C | Page 2 of 26 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack UP/DOWN INTERFACE Truth Table LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE INPUT SYSTEM OUTPUT AMPLIFIER GAIN CONTROL APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
ADL5201 Data Sheet TABLE OF CONTENTS
Features .. 1 Logic Timing ... 16 Applications ... 1 Circuit Description... 17 Functional Block Diagram .. 1 Basic Structure .. 17 General Description ... 1 Input System ... 17 Revision History ... 2 Output Amplifier .. 17 Specifications ... 3 Gain Control ... 17 Timing Diagrams .. 4 Applications Information .. 18 Absolute Maximum Ratings .. 5 Basic Connections .. 18 ESD Caution .. 5 ADC Driving ... 18 Pin Configuration and Function Descriptions ... 6 Layout Considerations ... 20 Typical Performance Characteristics ... 7 Evaluation Board .. 21 Characterization and Test Circuits ... 14 Evaluation Board Control Software ... 21 Theory of Operation .. 15 Schematics and Artwork ... 22 Digital Interface Overview .. 15 Evaluation Board Configuration Options ... 24 Parallel Digital Interface .. 15 Outline Dimensions ... 26 Serial Peripheral Interface (SPI) ... 15 Ordering Guide .. 26 Up/Down Interface .. 15
REVISION HISTORY 1/15—Rev. B to Rev. C
Changes to Table 1 .. 4 Change to Table 3 ... 6
9/13—Rev. A to Rev. B
Changed Logic Pins Absolute Maximum Rating from 3.6 V to −0.3 V to +3.6 V (not to exceed |VPOS − 0.5 V| at any time) .. 5
12/12—Rev. 0 to Rev. A
Changes to Layout Consideration Section .. 20 Updated Outline Dimensions ... 26
10/11—Revision 0: Initial Version
Rev. C | Page 2 of 26 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack UP/DOWN INTERFACE Truth Table LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE INPUT SYSTEM OUTPUT AMPLIFIER GAIN CONTROL APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE
