Datasheet ADL5310 (Analog Devices) - 3

Data Sheet ADL5310 SPECIFICATIONS
VP = 5 V, VN = 0 V, TA = 25°C, RREF = 665 kΩ, and VRDZ connected to VREF, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
INPUT INTERFACE Pin 1 to Pin 6: INP1 and INP2, IRF1 and IRF2, VSUM Specified Current Range, IPD Flows toward INP1 pin or INP2 pin 3 n 3 m A Input Current Min/Max Limits Flows toward INP1 pin or INP2 pin 10 m A Reference Current, IREF, Range Flows toward IRF1 pin or IRF2 pin 3 n 3 m A Summing Node Voltage Internally preset; user alterable 0.46 0.5 0.54 V Temperature Drift –40°C < TA < +85°C 0.030 mV/°C Input Offset Voltage VIN − VSUM, VIREF − VSUM −20 +20 mV LOGARITHMIC OUTPUTS Pin 15 and Pin 16: LOG1 and LOG2 Logarithmic Slope 190 200 210 mV/dec –40°C < TA < +85°C 185 215 mV/dec Logarithmic Intercept1 165 300 535 pA –40°C < TA < +85°C 40 1940 pA Law Conformance Error 10 nA < IPD < 1 mA 0.1 0.4 dB 3 nA < IPD < 3 mA 0.3 0.6 dB Wideband Noise2 IPD > 3 µA; output referred 0.5 µV/√Hz Small Signal Bandwidth2 IPD = 3 µA 1.5 MHz Maximum Output Voltage 1.7 V Minimum Output Voltage Limited by VN = 0 V 0.10 V Output Resistance 4.375 5 5.625 kΩ REFERENCE OUTPUT Pin 7 and Pin 24 (internally shorted): VREF Voltage wrt Ground 2.45 2.5 2.55 V –40°C < TA < +85°C 2.42 2.58 V Maximum Output Current Sourcing (grounded load) 20 mA Incremental Output Resistance Load current < 10 mA 4 Ω OUTPUT BUFFERS Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1, and OUT1 Input Offset Voltage −20 +20 mV Input Bias Current Flowing out of Pins 13, 14, 17, and 18 0.4 µA Incremental Input Resistance 35 MΩ Incremental Output Resistance Load current < 10 mA; gain = 1 0.5 Ω Output High Voltage RL = 1 kΩ to ground VP − 0.1 V Output Low Voltage RL = 1 kΩ to ground 0.10 V Peak Source/Sink Current 30 mA Small-Signal Bandwidth Gain = 1 15 MHz Slew Rate 0.2 V to 4.8 V output swing 15 V/µs POWER SUPPLY Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG Positive Supply Voltage (VP – VN ) ≤ 12 V 3 5 12 V Quiescent Current Input currents < 10 µA 9.5 11.5 mA Negative Supply Voltage (Optional) (VP – VN ) ≤ 12 V −5.5 0 V 1 Other values of logarithmic intercept can be achieved by adjustment of RREF. 2 Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1. Rev. B | Page 3 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS GENERAL STRUCTURE THEORY MANAGING INTERCEPT AND SLOPE RESPONSE TIME AND NOISE CONSIDERATIONS APPLICATIONS INFORMATION CALIBRATION MINIMIZING CROSSTALK RELATIVE AND ABSOLUTE POWER MEASUREMENTS CHARACTERIZATION METHODS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE