Datasheet AD8304 (Analog Devices) - 18

AD8304 HP 3577A HP 89410A NETWORK ANALYZER CHANNEL CHANNEL OUTPUT INPUT INPUTA INPUTB SOURCE TRIGGER 1 2 AD8304 POWER SPLITTER AD8304 1 VNEG ACOM 14 1 VNEG ACOM 14 2 PWDN BFNG 13 2 PWDN BFNG 3 VSUM VPS1 12 +IN 13 +V R1 AD8138 B S 3 VSUM VPS1 12 4 INPT VOUT 11 ALKALINE EVALUATION R1 D CELL 4 INPT VOUT 0.1 F 5 VSUM VPS2 10 BOARD A 11 750 5 VSUM VPS2 10 6 VPDB BFIN 9 750 1nF ALKALINE D CELL 6 VPDB BFIN 9 7 VREF VLOG 8 1nF 7 VREF VLOG 8
Figure 20. Configuration for Logarithmic Figure 21. Configuration for Noise Spectral Amplifier Bandwidth Measurement Density Measurement The setup shown in Figure 20 was used for frequency response
Evaluation Board
measurements of the logarithmic amplifier section. In this con- An evaluation board is available for the AD8304, the schematic figuration, the AD8138 output was offset to 1.5 V and R1 was for which is shown in Figure 22, and the two board sides are adjusted to provide the appropriate operating current. The shown in Figure 23 and Figure 24. It can be configured for a wide buffer amplifier was then used; still any capacitance added at variety of experiments. The board is factory set for Photocon- the VLOG Pin during measurement would form a filter with the ductive Mode with a buffer gain of unity, providing a slope of on-chip 5 kΩ resistor. 10 mV/dB and an intercept of 100 pA. By substituting resistor and The configuration illustrated in Figure 21 measures the device capacitor values, all of the application circuits presented in this noise. Batteries provide both the supply and the input signal to data sheet can be evaluated. Table V describes the various configu- remove the supplies as a possible noise source and to reduce ration options. ground loop effects. The AD8304 Evaluation Board and the current setting resistors are mounted in closed aluminum enclo- sures to provide additional shielding to external noise sources.
+VS GND –VS AD8304 R10 10k 1 VNEG ACOM 14 C1 C2 R1 0.1nF 1nF OPEN 2 PWDN BFNG 13 SW1 R7 R5 R2 OPEN OPEN 0 3 VSUM VPS1 12 C3 C4 BUFFER LK2 OPEN 1nF 0.1 F R13 R7 OUT 4 INPUT INPT VOUT 11 0 R15 OPEN LK1 750 C8 INSTALLED C11 5 VSUM VPS2 10 C7 R12 OPEN 1nF R9 R6 R11 OPEN OPEN 0.1 F OPEN 0 6 VPDB BFIN 9 C10 LOG R14 BIASER 0.1 F OUT 0 7 VREF VLOG 8 C9 C6 C5 10nF OPEN OPEN R4 OPEN R3 OPEN
Figure 22. Evaluation Board Schematic –18– REV. A Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS ORDERING GUIDE Typical Performance Characteristics BASIC CONCEPTS Optical Measurements Decibel Scaling GENERAL STRUCTURE Bandwidth and Noise Considerations Chip Enable USING THE AD8304 Slope and Intercept Adjustments Low Supply Slope and Intercept Adjustment Using the Adaptive Bias Changing the Voltage at the Summing Node Implementing Low-Pass Filters Operation in Comparator Modes Using a Negative Supply APPLICATIONS Summing Node at Ground and Voltage Inputs Providing Negative Outputs and Rescaling Inverting the Slope Programmable Level Comparator with Hysteresis Programmable Multidecade Current Source Characterization Setups and Methods Evaluation Board OUTLINE DIMENSIONS Revision History