Datasheet SSM2603 (Analog Devices) - 22

SSM2603 Data Sheet RIGHT-CHANNEL DAC VOLUME, ADDRESS 0x03 Table 17. Right-Channel DAC Volume Register Bit Map D8 D7 D6 D5 D4 D3 D2 D1 D0
RLHPBOTH 0 RHPVOL[6:0]
Table 18. Descriptions of Right-Channel DAC Volume Register Bits Bit Name Description Settings
RLHPBOTH Right-to-left headphone volume load control 0 = disable simultaneous loading of right-channel headphone volume data to left-channel register (default) 1 = enable simultaneous loading of right-channel headphone volume data to left-channel register RHPVOL[6:0] Right-channel headphone volume control 000 0000 to 010 1111 = mute 011 0000 = −73 dB … In 1 dB steps 111 1001 = 0 dB (default) … In 1 dB steps 111 1111 = +6 dB
ANALOG AUDIO PATH, ADDRESS 0x04 Table 19. Analog Audio Path Register Bit Map D8 D7 D6 D5 D4 D3 D2 D1 D0
0 SIDETONE_ATT[1:0] SIDETONE_EN DACSEL Bypass INSEL MUTEMIC MICBOOST
Table 20. Descriptions of Analog Audio Path Register Bits Bit Name Description Settings
SIDETONE_ATT[1:0] Microphone sidetone gain control. 00 = −6 dB (default) 01 = −9 dB 10 = −12 dB 11 = −15 dB SIDETONE_EN Sidetone enable. Allows attenuated microphone signal to 0 = sidetone disable (default) be mixed at device output terminal. 1 = sidetone enable DACSEL DAC select. Allows DAC output to be mixed at device 0 = do not select DAC (default) output terminal. 1 = select DAC Bypass Bypass select. Allows line input signal to be mixed at 0 = bypass disable device output terminal. 1 = bypass enable (default) INSEL Line input or microphone input select to ADC. 0 = line input select to ADC (default) 1 = microphone input select to ADC MUTEMIC Microphone mute control to ADC. 0 = mute on data path to ADC disable 1 = mute on data path to ADC enable (default) MICBOOST Primary microphone amplifier gain booster control. 0 = 0 dB (default) 1 = 20 dB
DIGITAL AUDIO PATH, ADDRESS 0x05 Table 21. Digital Audio Path Register Bit Map D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 HPOR DACMU DEEMPH[1:0] ADCHPF
Table 22. Descriptions of Digital Audio Path Register Bits Bit Name Description Settings
HPOR Stores dc offset when high-pass filter is disabled 0 = clear offset (default) 1 = store offset Rev. D | Page 22 of 31 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core Clock ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Hardware Mute Pin Automatic Level Control (ALC) Decay (Gain Ramp-Up) Time Attack (Gain Ramp-Down) Time Noise Gate Analog Interface Signal Chain Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Left-Channel DAC Volume, Address 0x02 Right-Channel DAC Volume, Address 0x03 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F ALC Control 1, Address 0x10 ALC Control 2, Address 0x11 Noise Gate, Address 0x12 Outline Dimensions Ordering Guide