Datasheet ADT7310 (Analog Devices) - 20

ADT7310 Data Sheet CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 22 23 24 8-BIT COMMAND BYTE CONT 0 R/W REGISTER ADDR 0 0 READ DIN C7 C6 C5 C4 C3 C2 C1 C0 16-BIT DATA
031
DOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D2 D1 D0
07789- Figure 21. Read from a 16-Bit Register
READING DATA
DSPs. SCLK can continue to run between data transfers, provided that the timing numbers are obeyed. A read transaction begins when the master writes the command byte to the ADT7310 with the read/write bit set to 1. The master CS can be tied to ground, and the serial interface can be then supplies 8 or 16 clock pulses, depending on the addressed operated in a 3-wire mode. DIN, DOUT, and SCLK are register, and the ADT7310 clocks out data from the addressed used to communicate with the ADT7310 in this mode. register on the DOUT line. Data is clocked out on the first falling edge of SCLK following the command byte. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. The read transaction finishes when the master takes CS high.
SERIAL INTERFACE RESET
The master must begin a new read transaction on the bus for The serial interface can be reset by writing a series of 1s on the every register read. Only one register is read per bus transaction. DIN input. If a Logic 1 is written to the ADT7310 line for at However, in continuous read mode, Command Byte C2 = 1, and least 32 serial clock cycles, the serial interface is reset. This the temperature value register can be read from continuously. ensures that the interface can be reset to a known state if the The master sends 16 clock pulses on SCLK, and the temperature interface gets lost due to a software error or some glitch in the value is clocked out on DOUT. system. Reset returns the interface to the state in which it is
INTERFACING TO DSPs OR MICROCONTROLLERS
expecting a write to the communications register. This opera- tion resets the contents of al registers to their power-on values. The ADT7310 can be operated with CS used as a frame syn- Following a reset, the user should allow a period of 500 µs chronization signal. This scheme is useful for DSP interfaces. before addressing the serial interface. In this case, the first bit (MSB) is effectively clocked out by CS because CS normally occurs after the falling edge of SCLK in Rev. A | Page 20 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications SPI Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Circuit Information Converter Details Temperature Measurement One-Shot Mode 1 SPS Mode CT and INT Operation in One-Shot Mode Continuous Read Mode Shutdown Fault Queue Temperature Data Format Temperature Conversion Formulas 16-Bit Temperature Data Format 13-Bit Temperature Data Format 10-Bit Temperature Data Format 9-Bit Temperature Data Format Registers Status Register Configuration Register Temperature Value Register ID Register TCRIT Setpoint Register THYST Setpoint Register THIGH Setpoint Register TLOW Setpoint Register Serial Interface SPI Command Byte Writing Data Reading Data Interfacing to DSPs or Microcontrollers Serial Interface Reset INT and CT Outputs Undertemperature and Overtemperature Detection Comparator Mode Interrupt Mode Applications Information Thermal Response Time Supply Decoupling Temperature Monitoring Outline Dimensions Ordering Guide