Datasheet SSD1306 (Solomon Systech) - 43
| Manufacturer | Solomon Systech |
| Description | 128 x 64, Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| Pages / Page | 64 / 43 — 10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h). … |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h). Figure 10-7 : Oscillator frequency setting
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10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)
This command consists of two functions: • Display Clock Divide Ratio (D)(A[3:0]) Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16, with reset value = 1. Please refer to section 8.3 for the details relationship of DCLK and CLK. • Oscillator Frequency (A[7:4]) Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high. The 4-bit value results in 16 different frequency settings available as shown below. The default setting is 1000b.
Figure 10-7 : Oscillator frequency setting Oscillator Freqeuncy vs D5h (A[7:4]) command setting
700 600
)
500
z kH
400
cy ( en u
300
req F
200 100 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
D5h (A[7:4]) command setting 10.1.17 Set Pre-charge Period (D9h)
This command is used to set the duration of the pre-charge period. The interval is counted in number of DCLK, where RESET equals 2 DCLKs.
SSD1306
Rev 1.5 P 43/64 Aug 2010
Solomon Systech
Document Outline 1 GENERAL DESCRIPTION 2 FEATURES 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 DIE PAD FLOOR PLAN 6 PIN ARRANGEMENT 6.1 SSD1306TR1 pin assignment 7 PIN DESCRIPTION 8 FUNCTIONAL BLOCK DESCRIPTIONS 8.1 MCU Interface selection 8.1.1 MCU Parallel 6800-series Interface 8.1.2 MCU Parallel 8080-series Interface 8.1.3 MCU Serial Interface (4-wire SPI) 8.1.4 MCU Serial Interface (3-wire SPI) 8.1.5 MCU I2C Interface 8.1.5.1 I2C-bus Write data 8.1.5.2 Write mode for I2C 8.2 Command Decoder 8.3 Oscillator Circuit and Display Time Generator 8.4 FR synchronization 8.5 Reset Circuit 8.6 Segment Drivers / Common Drivers 8.7 Graphic Display Data RAM (GDDRAM) 8.8 SEG/COM Driving block 8.9 Power ON and OFF sequence 8.9.1 Power ON and OFF sequence with External VCC 8.9.2 Power ON and OFF sequence with Charge Pump Application 8.10 Charge Pump Regulator 9 COMMAND TABLE 9.1 Data Read / Write 10 COMMAND DESCRIPTIONS 10.1 Fundamental Command 10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) 10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh) 10.1.3 Set Memory Addressing Mode (20h) 10.1.4 Set Column Address (21h) 10.1.5 Set Page Address (22h) 10.1.6 Set Display Start Line (40h~7Fh) 10.1.7 Set Contrast Control for BANK0 (81h) 10.1.8 Set Segment Re-map (A0h/A1h) 10.1.9 Entire Display ON (A4h/A5h) 10.1.10 Set Normal/Inverse Display (A6h/A7h) 10.1.11 Set Multiplex Ratio (A8h) 10.1.12 Set Display ON/OFF (AEh/AFh) 10.1.13 Set Page Start Address for Page Addressing Mode (B0h~B7h) 10.1.14 Set COM Output Scan Direction (C0h/C8h) 10.1.15 Set Display Offset (D3h) 10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) 10.1.17 Set Pre-charge Period (D9h) 10.1.18 Set COM Pins Hardware Configuration (DAh) 10.1.19 Set VCOMH Deselect Level (DBh) 10.1.20 NOP (E3h) 10.1.21 Status register Read 10.1.22 Charge Pump Setting (8Dh) 10.2 Graphic Acceleration Command 10.2.1 Horizontal Scroll Setup (26h/27h) 10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah) 10.2.3 Deactivate Scroll (2Eh) 10.2.4 Activate Scroll (2Fh) 10.2.5 Set Vertical Scroll Area(A3h) 10.3 Advance Graphic Command 10.3.1 Set Fade Out and Blinking (23h) 10.3.2 Set Zoom In (D6h) 11 MAXIMUM RATINGS 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 14 Application Example 15 PACKAGE INFORMATION 15.1 SSD1306TR1 Detail Dimension 15.2 SSD1306Z2 Die Tray Information
10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)
This command consists of two functions: • Display Clock Divide Ratio (D)(A[3:0]) Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16, with reset value = 1. Please refer to section 8.3 for the details relationship of DCLK and CLK. • Oscillator Frequency (A[7:4]) Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high. The 4-bit value results in 16 different frequency settings available as shown below. The default setting is 1000b.
Figure 10-7 : Oscillator frequency setting Oscillator Freqeuncy vs D5h (A[7:4]) command setting
700 600
)
500
z kH
400
cy ( en u
300
req F
200 100 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
D5h (A[7:4]) command setting 10.1.17 Set Pre-charge Period (D9h)
This command is used to set the duration of the pre-charge period. The interval is counted in number of DCLK, where RESET equals 2 DCLKs.
SSD1306
Rev 1.5 P 43/64 Aug 2010
Solomon Systech
Document Outline 1 GENERAL DESCRIPTION 2 FEATURES 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 DIE PAD FLOOR PLAN 6 PIN ARRANGEMENT 6.1 SSD1306TR1 pin assignment 7 PIN DESCRIPTION 8 FUNCTIONAL BLOCK DESCRIPTIONS 8.1 MCU Interface selection 8.1.1 MCU Parallel 6800-series Interface 8.1.2 MCU Parallel 8080-series Interface 8.1.3 MCU Serial Interface (4-wire SPI) 8.1.4 MCU Serial Interface (3-wire SPI) 8.1.5 MCU I2C Interface 8.1.5.1 I2C-bus Write data 8.1.5.2 Write mode for I2C 8.2 Command Decoder 8.3 Oscillator Circuit and Display Time Generator 8.4 FR synchronization 8.5 Reset Circuit 8.6 Segment Drivers / Common Drivers 8.7 Graphic Display Data RAM (GDDRAM) 8.8 SEG/COM Driving block 8.9 Power ON and OFF sequence 8.9.1 Power ON and OFF sequence with External VCC 8.9.2 Power ON and OFF sequence with Charge Pump Application 8.10 Charge Pump Regulator 9 COMMAND TABLE 9.1 Data Read / Write 10 COMMAND DESCRIPTIONS 10.1 Fundamental Command 10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) 10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh) 10.1.3 Set Memory Addressing Mode (20h) 10.1.4 Set Column Address (21h) 10.1.5 Set Page Address (22h) 10.1.6 Set Display Start Line (40h~7Fh) 10.1.7 Set Contrast Control for BANK0 (81h) 10.1.8 Set Segment Re-map (A0h/A1h) 10.1.9 Entire Display ON (A4h/A5h) 10.1.10 Set Normal/Inverse Display (A6h/A7h) 10.1.11 Set Multiplex Ratio (A8h) 10.1.12 Set Display ON/OFF (AEh/AFh) 10.1.13 Set Page Start Address for Page Addressing Mode (B0h~B7h) 10.1.14 Set COM Output Scan Direction (C0h/C8h) 10.1.15 Set Display Offset (D3h) 10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) 10.1.17 Set Pre-charge Period (D9h) 10.1.18 Set COM Pins Hardware Configuration (DAh) 10.1.19 Set VCOMH Deselect Level (DBh) 10.1.20 NOP (E3h) 10.1.21 Status register Read 10.1.22 Charge Pump Setting (8Dh) 10.2 Graphic Acceleration Command 10.2.1 Horizontal Scroll Setup (26h/27h) 10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah) 10.2.3 Deactivate Scroll (2Eh) 10.2.4 Activate Scroll (2Fh) 10.2.5 Set Vertical Scroll Area(A3h) 10.3 Advance Graphic Command 10.3.1 Set Fade Out and Blinking (23h) 10.3.2 Set Zoom In (D6h) 11 MAXIMUM RATINGS 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 14 Application Example 15 PACKAGE INFORMATION 15.1 SSD1306TR1 Detail Dimension 15.2 SSD1306Z2 Die Tray Information