Datasheet KSZ8462HLI, KSZ8462FHLI (Microchip) - 8
| Manufacturer | Microchip |
| Description | IEEE 1588 Precision Time Protocol-Enabled, Two-Port, 10/100 Mbps Ethernet Switch with 8-or 16-Bit Host Interface |
| Pages / Page | 233 / 8 — KSZ8462HLI/FHLI. FIGURE 1-2:. SYSTEM BLOCK DIAGRAM, KSZ8462HLI/FHLI |
| File Format / Size | PDF / 2.4 Mb |
| Document Language | English |
KSZ8462HLI/FHLI. FIGURE 1-2:. SYSTEM BLOCK DIAGRAM, KSZ8462HLI/FHLI
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KSZ8462HLI/FHLI FIGURE 1-2: SYSTEM BLOCK DIAGRAM, KSZ8462HLI/FHLI
EEPROM 1024 INTERFACE FRAME QUEUE EEPROM MIB BUFFERS ADDRESSES MANAGEMENT INTERFACE COUNTERS MANAGEMENT LOOK-UP TABLE SWITCH ENGINE VLAN TAGGING, QoS PRIORITY, FIFO, FLOW CONTROL IEEE 1588 PTP PACKET FILTERING AND PROCESSING VDD_IO 1.3V LOW-NOISE VDD_L IEEE 1588 TIME REGULATOR STAMP FOR PORT 1 IEEE 1588 INTRN ENABLED PORT 1 IEEE 1588 HOST MAC 10/100 BASE TX/RX ± ENABLED SD[15:0] 10/100 T/TX/FX MAC 1 PHY1 (AUTO MDI/MDI-X) CMD TXQ IEEE 1588 NON-PCI QMU 10/100 BASE 6KB ENABLED RDN SHARED AND T/TX/FX 10/100 DATA BUS DMA PHY2 MAC 2 PORT 2 WRN INTERFACE RXQ CONTROL TX/RX ± UNIT 12KB CSN IEEE 1588 TIME STAMP FOR PORT 2 X1 LINK MD AND X2 PLL CLOCK (TO 1588 TIME I/O REGISTERS ENERGY-EFFICIENT STAMP BLOCKS) CONTROL/STATUS ETHERNET CONTROL IEEE 1588 POWER PME SYNCHRONIZED MANAGEMENT CLOCK P1LED[1:0] GPIOs 12 EVENT TRIGGER UNITS AND LED DRIVER P2LED[1:0] 12 TIMESTAMP UNITS DS00002641A-page 8
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 Media Access Controller (MAC) Block 3.4 Switch Block 3.5 Queue Management Unit (QMU) 3.6 IEEE 1588 Precision Time Protocol (PTP) Block 3.7 General Purpose and IEEE 1588 Input/Output (GPIO) 3.8 Using the GPIO Pins with the Trigger Output Units 3.9 Using the GPIO Pins with the Time Stamp Input Units 3.10 Device Clocks 3.11 Power 3.12 Power Management 3.13 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 Management Information Base (MIB) Counters 4.4 Static MAC Address Table 4.5 Dynamic MAC Address Table 4.6 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read/Write Timing 7.2 Auto-Negotiation Timing 7.3 Trigger Output Unit and Time Stamp Input Unit Timing 7.4 Serial EEPROM Interface Timing 7.5 Reset and Power Sequence Timing 7.6 Reset Circuit Guidelines 8.0 Reference Circuit: LED Strap-In Pins 9.0 Reference Clock: Connection and Selection 10.0 Selection of Isolation Transformers 11.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
EEPROM 1024 INTERFACE FRAME QUEUE EEPROM MIB BUFFERS ADDRESSES MANAGEMENT INTERFACE COUNTERS MANAGEMENT LOOK-UP TABLE SWITCH ENGINE VLAN TAGGING, QoS PRIORITY, FIFO, FLOW CONTROL IEEE 1588 PTP PACKET FILTERING AND PROCESSING VDD_IO 1.3V LOW-NOISE VDD_L IEEE 1588 TIME REGULATOR STAMP FOR PORT 1 IEEE 1588 INTRN ENABLED PORT 1 IEEE 1588 HOST MAC 10/100 BASE TX/RX ± ENABLED SD[15:0] 10/100 T/TX/FX MAC 1 PHY1 (AUTO MDI/MDI-X) CMD TXQ IEEE 1588 NON-PCI QMU 10/100 BASE 6KB ENABLED RDN SHARED AND T/TX/FX 10/100 DATA BUS DMA PHY2 MAC 2 PORT 2 WRN INTERFACE RXQ CONTROL TX/RX ± UNIT 12KB CSN IEEE 1588 TIME STAMP FOR PORT 2 X1 LINK MD AND X2 PLL CLOCK (TO 1588 TIME I/O REGISTERS ENERGY-EFFICIENT STAMP BLOCKS) CONTROL/STATUS ETHERNET CONTROL IEEE 1588 POWER PME SYNCHRONIZED MANAGEMENT CLOCK P1LED[1:0] GPIOs 12 EVENT TRIGGER UNITS AND LED DRIVER P2LED[1:0] 12 TIMESTAMP UNITS DS00002641A-page 8
2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 Media Access Controller (MAC) Block 3.4 Switch Block 3.5 Queue Management Unit (QMU) 3.6 IEEE 1588 Precision Time Protocol (PTP) Block 3.7 General Purpose and IEEE 1588 Input/Output (GPIO) 3.8 Using the GPIO Pins with the Trigger Output Units 3.9 Using the GPIO Pins with the Time Stamp Input Units 3.10 Device Clocks 3.11 Power 3.12 Power Management 3.13 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 Management Information Base (MIB) Counters 4.4 Static MAC Address Table 4.5 Dynamic MAC Address Table 4.6 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read/Write Timing 7.2 Auto-Negotiation Timing 7.3 Trigger Output Unit and Time Stamp Input Unit Timing 7.4 Serial EEPROM Interface Timing 7.5 Reset and Power Sequence Timing 7.6 Reset Circuit Guidelines 8.0 Reference Circuit: LED Strap-In Pins 9.0 Reference Clock: Connection and Selection 10.0 Selection of Isolation Transformers 11.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
