Datasheet KSZ8842-16M, KSZ8842-32M (Microchip)

ManufacturerMicrochip
DescriptionTwo-Port Ethernet Switch with Non-PCI Interface
Pages / Page132 / 1 — KSZ8842-16M/-32M. Two-Port Ethernet Switch with Non-PCI Interface. …
File Format / SizePDF / 3.0 Mb
Document Languageenglish

KSZ8842-16M/-32M. Two-Port Ethernet Switch with Non-PCI Interface. Features. Switch Management. Advanced Switch Management

Datasheet KSZ8842-16M, KSZ8842-32M Microchip

Model Line for this Datasheet

Text Version of Document

KSZ8842-16M/-32M Two-Port Ethernet Switch with Non-PCI Interface Features
• Per Port-Based, Software Power-Save on PHY (Idle Link Detection, Register Configuration Pre-
Switch Management
served) • Non-Blocking Switch Fabric Assures Fast Packet • Single Power Supply: 3.3V Delivery by Utilizing a 1K Entry Forwarding Table • Commercial Temperature Range: 0°C to +70°C and a Store-and-Forward Architecture • Industrial Temperature Range: –40°C to +85°C • Fully Compliant with IEEE 802.3u Standards • Available in 128-pin PQFP, 100-ball LFBGA, and • Full-Duplex IEEE 802.3x Flow Control (Pause) 128-pin LQFP with Force Mode Option • Available in -16 Version for 8/16-Bit Bus Support • Half-Duplex Back Pressure Flow Control and -32 version for 32-Bit Bus Support
Advanced Switch Management Additional Features
• IEEE 802.1Q VLAN Support for Up to 16 Groups In Addition to Offering All of the Features of an Inte- (Full Range of VLAN IDs) grated Layer-2 Managed Switch, the KSZ8842M • VLAN ID Tag/Untag Options, on a Per Port Basis Offers: • IEEE 802.1p/Q Tag Insertion or Removal on a Per • Repeater Mode Capabilities to Allow for Cut Port Basis (Egress) Through in Latency Critical Industrial Ethernet or • Programmable Rate Limiting at the Ingress and Embedded Ethernet Applications Egress Ports • Dynamic Buffer Memory Scheme • Broadcast Storm Protection - Essential for Applications Such as Video over • IEEE 802.1d Spanning Tree Protocol Support IP where Image Jitter is Unacceptable • MAC Filtering Function to Filter or Forward • 2-Port Switch with a Flexible 8-Bit, 16-Bit, or 32- Unknown Unicast Packets Bit Generic Host Processor Interfaces • Direct Forwarding Mode Enabling the Processor • Microchip LinkMD® Cable Diagnostic to Deter- to Identify the Ingress Port and to Specify the mine Cable Length, Diagnose Faulty Cables, and Egress Port Determine Distance to Fault • Internet Group Management Protocol (IGMP) v1/ • Hewlett Packard (HP) Auto-MDIX Crossover with v2 Snooping Support for Multicast Packet Filtering Disable and Enable Options • IPV6 Multicast Listener Discovery (MLD) Snoop- • Four Priority Queues to Handle Voice, Video, ing Support Data, and Control Packets
Monitoring
• Ability to Transmit and Receive Frames up to • Port Mirroring/Monitoring/Sniffing: Ingress and/or 1916 bytes Egress Traffic to Any Port
Applications
• MIB Counters for Fully Compliant Statistics Gath- • Video Distribution Systems ering - 34 MIB Counters Per Port • High-End Cable, Satellite, and IP Set-Top Boxes • Loopback Modes for Remote Failure Diagnostics • Video over IP
Comprehensive Register Access
• Voice over IP (VoIP) and Analog Telephone • Control Registers Configurable On-the-Fly (Port- Adapters (ATA) Priority, 802.1p/d/Q) • Industrial Control in Latency Critical Applications
QoS/CoS Packets Prioritization Support
• Motion Control • Per Port, 802.1p and DiffServ-Based • Industrial Control Sensor Devices (Temperature, Pressure, Levels, and Valves) • Remapping of 802.1p Priority Field on a Per Port Basis • Security and Surveillance Cameras
Power Modes, Packaging, and Power Supplies Markets
• Full-Chip Hardware Power-Down (Register Con- • Fast Ethernet figuration not Saved) Allows Low Power Dissipa- • Embedded Ethernet tion • Industrial Ethernet  2020 Microchip Technology Inc.

DS00003459A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Free Shipping for All PCB Assembly Order