Datasheet KSZ8842-16M, KSZ8842-32M (Microchip) - 6
| Manufacturer | Microchip |
| Description | Two-Port Ethernet Switch with Non-PCI Interface |
| Pages / Page | 132 / 6 — KSZ8842-16M/-32M. FIGURE 2-2:. PIN CONFIGURATION FOR KSZ8842-16MVL |
| File Format / Size | PDF / 3.0 Mb |
| Document Language | English |
KSZ8842-16M/-32M. FIGURE 2-2:. PIN CONFIGURATION FOR KSZ8842-16MVL
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KSZ8842-16M/-32M FIGURE 2-2: PIN CONFIGURATION FOR KSZ8842-16MVL
O N N 0 1 2 3 4 5 N T DDC DDI NC NC NC NC VDDIO V DGND NC BE0 BE1 NC NC A1 A2 A3 A4 A5 V DGND A6 A7 A8 A9 A1 A1 A1 A1 A1 A1 RS X2 X1 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 NC 97 64 AGND NC 98 63 VDDAP NC 99 62 AGND NC 100 61 ISET NC 101 60 NC NC 102 59 103 NC NC 58 AGND 104 NC 57 VDDA 105 NC 56 TXP2 106 NC 55 TXM2 107 DGND 54 AGND 108 VDDIO 53 RXP2 109 NC 52 RXM2 110 D15 51 VDDARX 111 D14 KSZ8842-16MVL 50 VDDATX 112 D13 49 TXM1 113 D12 (Top View) 48 TXP1 114 D11 47 AGND D10 115 46 RXM1 D9 116 45 RXP1 D8 117 44 NC D7 118 43 VDDA D6 119 42 AGND D5 120 41 NC D4 121 40 NC D3 122 39 DGND 123 AGND 38 VDDA DGND 124 37 AGND VDDIO 125 36 PWRDN D2 126 35 ADSN D1 127 34 DGND D0 128 33 WRN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 1 0 2 O D D N ED E E ED NC NC L L RDN EED EESK EEDI SWR AEN BCLK ARDY EEE VDDIO SRDYN INTRN LDEVN EECS DGND TESTEN SCANEN P1 P1L P1L P2 P2LED1 P2LED0 DGND P1LED3 CYCLEN P2LED3 VDDCO VLBUSN RDYRTNN DS00003459A-page 6
2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
O N N 0 1 2 3 4 5 N T DDC DDI NC NC NC NC VDDIO V DGND NC BE0 BE1 NC NC A1 A2 A3 A4 A5 V DGND A6 A7 A8 A9 A1 A1 A1 A1 A1 A1 RS X2 X1 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 NC 97 64 AGND NC 98 63 VDDAP NC 99 62 AGND NC 100 61 ISET NC 101 60 NC NC 102 59 103 NC NC 58 AGND 104 NC 57 VDDA 105 NC 56 TXP2 106 NC 55 TXM2 107 DGND 54 AGND 108 VDDIO 53 RXP2 109 NC 52 RXM2 110 D15 51 VDDARX 111 D14 KSZ8842-16MVL 50 VDDATX 112 D13 49 TXM1 113 D12 (Top View) 48 TXP1 114 D11 47 AGND D10 115 46 RXM1 D9 116 45 RXP1 D8 117 44 NC D7 118 43 VDDA D6 119 42 AGND D5 120 41 NC D4 121 40 NC D3 122 39 DGND 123 AGND 38 VDDA DGND 124 37 AGND VDDIO 125 36 PWRDN D2 126 35 ADSN D1 127 34 DGND D0 128 33 WRN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 1 0 2 O D D N ED E E ED NC NC L L RDN EED EESK EEDI SWR AEN BCLK ARDY EEE VDDIO SRDYN INTRN LDEVN EECS DGND TESTEN SCANEN P1 P1L P1L P2 P2LED1 P2LED0 DGND P1LED3 CYCLEN P2LED3 VDDCO VLBUSN RDYRTNN DS00003459A-page 6
2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
