Datasheet KSZ8993 (Microchip) - 4
| Manufacturer | Microchip |
| Description | 3-Port 10/100 Integrated Switch with PHY and Frame Buffer |
| Pages / Page | 35 / 4 — Table of Contents. System Level Applications .. Pin Description. I/O … |
| File Format / Size | PDF / 231 Kb |
| Document Language | English |
Table of Contents. System Level Applications .. Pin Description. I/O Grouping. I/O Descriptions. Pin Configuration ..
Model Line for this Datasheet
Text Version of Document
KS8993 Micrel
Table of Contents System Level Applications ..
5
Pin Description
.. 6
I/O Grouping
.. 9
I/O Descriptions
.. 10
Pin Configuration ...
15
Functional Overview: Physical Layer Transceiver ...
16 100BaseTX Transmit ... 16 100BaseTX Receive .. 16 PLL Clock Synthesizer .. 16 Scrambler/De-scrambler (100BaseTX only) .. 16 100BaseFX operation .. 16 100BaseFX Signal Detection ... 16 100BaseFX Far End Fault ... 16 10BaseT Transmit ... 16 10BaseT Receive .. 16 Power Management .. 17 LED Mode Selection .. 17 Auto-Negotiation .. 17
Functional Overview: Switch Core ...
18 Address Look Up ... 18 Learning .. 18 Migration ... 18 Aging .. 18 Forwarding .. 18 Switching Engine ... 18 MAC (Media Access Controller) Operation ... 18 Inter Packet Group .. 18 Back off Algorithm ... 18 Late Collision .. 18 Illegal Frame ... 18 Flow Control .. 18 Full-Duplex Flow Control ... 18 Half-Duplex Back Pressure ... 18 VLAN Support .. 19 QoS Priority Support .. 20
MII Interface Operation ..
21
SNI Interface (7-wire) Operation ...
22
Absolute Maximum Ratings ..
23
Operating Ratings ..
23
Electrical Characteristics ..
23
Timing Diagrams ..
24
Reference Circuit ...
29
4B/5B Coding
.. 31
MLT Coding
.. 32
802.1q VLAN and 802.1p Priority Frame ..
33
Selection of Isolation Transformers ...
34
Selection of Reference Crystals ...
34
Package Outline and Dimensions ..
35 KS8993 4 May 2005
Table of Contents System Level Applications ..
5
Pin Description
.. 6
I/O Grouping
.. 9
I/O Descriptions
.. 10
Pin Configuration ...
15
Functional Overview: Physical Layer Transceiver ...
16 100BaseTX Transmit ... 16 100BaseTX Receive .. 16 PLL Clock Synthesizer .. 16 Scrambler/De-scrambler (100BaseTX only) .. 16 100BaseFX operation .. 16 100BaseFX Signal Detection ... 16 100BaseFX Far End Fault ... 16 10BaseT Transmit ... 16 10BaseT Receive .. 16 Power Management .. 17 LED Mode Selection .. 17 Auto-Negotiation .. 17
Functional Overview: Switch Core ...
18 Address Look Up ... 18 Learning .. 18 Migration ... 18 Aging .. 18 Forwarding .. 18 Switching Engine ... 18 MAC (Media Access Controller) Operation ... 18 Inter Packet Group .. 18 Back off Algorithm ... 18 Late Collision .. 18 Illegal Frame ... 18 Flow Control .. 18 Full-Duplex Flow Control ... 18 Half-Duplex Back Pressure ... 18 VLAN Support .. 19 QoS Priority Support .. 20
MII Interface Operation ..
21
SNI Interface (7-wire) Operation ...
22
Absolute Maximum Ratings ..
23
Operating Ratings ..
23
Electrical Characteristics ..
23
Timing Diagrams ..
24
Reference Circuit ...
29
4B/5B Coding
.. 31
MLT Coding
.. 32
802.1q VLAN and 802.1p Priority Frame ..
33
Selection of Isolation Transformers ...
34
Selection of Reference Crystals ...
34
Package Outline and Dimensions ..
35 KS8993 4 May 2005
