Datasheet KSZ8993 (Microchip) - 7
| Manufacturer | Microchip |
| Description | 3-Port 10/100 Integrated Switch with PHY and Frame Buffer |
| Pages / Page | 35 / 7 — Pin Number. Pin Name. Type(Note 1). Port. Pin Function. Note 1 |
| File Format / Size | PDF / 231 Kb |
| Document Language | English |
Pin Number. Pin Name. Type(Note 1). Port. Pin Function. Note 1
Model Line for this Datasheet
Text Version of Document
KS8993 Micrel
Pin Number Pin Name Type(Note 1) Port Pin Function
39 TEST[1] I Factory test pin 40 TEST[2] I Factory test pin 41 GND_RCV[2] GND 2 Ground for clock recovery circuitry 42 VDD_RCV[2] Pwr 2 2.5V for clock recovery circuitry 43 GND_RCV[3] GND 3 Ground for clock recovery circuitry 44 VDD_RCV[3] P 3 2.5V for clock recovery circuitry 45 VMDIS I DIScard VLAN Mismatch packets 46 FFLOW2# I 2 Force flow control on port 2 47 PV32 I 3 Port 3 VLAN Port mask bit 1 48 PV31 I 3 Port 3 VLAN Port mask bit 0 49 PV23 I 2 Port 2 VLAN Port mask bit 2 50 FFLOW1# I 1 Force flow control on port 1 51 PV21 I 2 Port 2 VLAN Port mask bit 0 52 PV13 I 1 Port 1 VLAN Port mask bit 2 53 PV12 I 1 Port 1 VLAN Port mask bit 1 54 DISAN3 I 3 Port 3 auto-negotiation disable (pull this down to enable port 3 auto negotiation) 55 VDD Pwr 2.5V for core digital circuitry 56 GND GND Ground for digital circuitry 57 MTXEN I 3 MII transmit enable 58 MTXD[3] I 3 MII transmit bit 3 59 MTXD[2] I 3 MII transmit bit 2 60 MTXD[1] I 3 MII transmit bit 1 61 MTXD[0] I 3 MII transmit bit 0 62 MTXER I 3 MII transmit error 63 MTXCLK I/O 3 MII output clock 64 MRXDV O 3 MII receive data valid 65 MRXD[3] O 3 MII receive bit 3 66 MRXD[2] O 3 MII receive bit 2 67 MRXD[1] O 3 MII receive bit 1 68 MRXD[0] O 3 MII receive bit 0 69 VDD_IO Pwr 2.5V or 3.3V for MII interface, LEDs and other digital I/O 70 GND GND Ground for digital circuitry 71 MRXCLK I/O 3 MII input clock 72 MCOL O 3 MII collision detect output 73 MCRS I/O 3 MII carrier sense 74 MCOLIN I 3 MII collision detect input 75 MIIS[1] I 3 MII mode select bit 1 76 MIIS[0] I 3 MII mode select bit 0
Note 1.
Pwr = power supply GND = ground I = input O = output I/O = bi-directional May 2005 7 KS8993
Pin Number Pin Name Type(Note 1) Port Pin Function
39 TEST[1] I Factory test pin 40 TEST[2] I Factory test pin 41 GND_RCV[2] GND 2 Ground for clock recovery circuitry 42 VDD_RCV[2] Pwr 2 2.5V for clock recovery circuitry 43 GND_RCV[3] GND 3 Ground for clock recovery circuitry 44 VDD_RCV[3] P 3 2.5V for clock recovery circuitry 45 VMDIS I DIScard VLAN Mismatch packets 46 FFLOW2# I 2 Force flow control on port 2 47 PV32 I 3 Port 3 VLAN Port mask bit 1 48 PV31 I 3 Port 3 VLAN Port mask bit 0 49 PV23 I 2 Port 2 VLAN Port mask bit 2 50 FFLOW1# I 1 Force flow control on port 1 51 PV21 I 2 Port 2 VLAN Port mask bit 0 52 PV13 I 1 Port 1 VLAN Port mask bit 2 53 PV12 I 1 Port 1 VLAN Port mask bit 1 54 DISAN3 I 3 Port 3 auto-negotiation disable (pull this down to enable port 3 auto negotiation) 55 VDD Pwr 2.5V for core digital circuitry 56 GND GND Ground for digital circuitry 57 MTXEN I 3 MII transmit enable 58 MTXD[3] I 3 MII transmit bit 3 59 MTXD[2] I 3 MII transmit bit 2 60 MTXD[1] I 3 MII transmit bit 1 61 MTXD[0] I 3 MII transmit bit 0 62 MTXER I 3 MII transmit error 63 MTXCLK I/O 3 MII output clock 64 MRXDV O 3 MII receive data valid 65 MRXD[3] O 3 MII receive bit 3 66 MRXD[2] O 3 MII receive bit 2 67 MRXD[1] O 3 MII receive bit 1 68 MRXD[0] O 3 MII receive bit 0 69 VDD_IO Pwr 2.5V or 3.3V for MII interface, LEDs and other digital I/O 70 GND GND Ground for digital circuitry 71 MRXCLK I/O 3 MII input clock 72 MCOL O 3 MII collision detect output 73 MCRS I/O 3 MII carrier sense 74 MCOLIN I 3 MII collision detect input 75 MIIS[1] I 3 MII mode select bit 1 76 MIIS[0] I 3 MII mode select bit 0
Note 1.
Pwr = power supply GND = ground I = input O = output I/O = bi-directional May 2005 7 KS8993
