Datasheet AD5592R-1-KGD (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 8 Channel, 12-Bit, Configurable ADC/DAC with on-chip Reference, SPI interface |
| Pages / Page | 10 / 6 — AD5592R-1-KGD. Known Good Die. Parameter. Min. Typ. Max. Unit1. Test … |
| File Format / Size | PDF / 201 Kb |
| Document Language | English |
AD5592R-1-KGD. Known Good Die. Parameter. Min. Typ. Max. Unit1. Test Conditions/Comments. TIMING CHARACTERISTICS. Table 2. Parameter
Model Line for this Datasheet
Text Version of Document
AD5592R-1-KGD Known Good Die Parameter Min Typ Max Unit1 Test Conditions/Comments
0.5 mA I/O0 to I/O7 are ADCs, external reference, gain = 1 0.45 mA I/O0 to I/O7 are general-purpose outputs 0.45 mA I/O0 to I/O7 are general-purpose inputs VLOGIC 1.62 VDD V ILOGIC 3 µA 1 All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted. 2 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of 10 mV when VREF = VDD. 3 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter 1.62 V ≤ VLOGIC < 3 V 3 V ≤ VLOGIC ≤ 5.5 V Unit Test Conditions/Comments
t1 33 20 ns min SCLK cycle time, write operation 65 50 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time t3 16 10 ns min SCLK low time t4 15 10 ns min SYNC to SCLK falling edge setup time 2 2 µs max SYNC to SCLK falling edge setup time t5 7 7 ns min Data setup time t6 5 5 ns min Data hold time t7 15 10 ns min SCLK falling edge to SYNC rising edge t8 30 30 ns min Minimum SYNC high time for write operations 60 60 ns min Minimum SYNC high time for register read operations t9 0 0 ns min SYNC rising edge to next SCLK falling edge t10 56 25 ns max SCLK rising edge to SDO valid
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
003
200µA IOH
15688- Figure 2. Load Circuit for Logic Output (SDO) Timing Specifications
t1 t9 SCLK t2 t t t3 t 8 4 7 SYNC t6 t5 SDI DB15 DB0 t10
004
SDO DB15 DB0
15688- Figure 3. Timing Diagram Rev. 0 | Page 6 of 10 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Die Specifications and Assembly Recommendations Ordering Guide
0.5 mA I/O0 to I/O7 are ADCs, external reference, gain = 1 0.45 mA I/O0 to I/O7 are general-purpose outputs 0.45 mA I/O0 to I/O7 are general-purpose inputs VLOGIC 1.62 VDD V ILOGIC 3 µA 1 All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted. 2 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of 10 mV when VREF = VDD. 3 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter 1.62 V ≤ VLOGIC < 3 V 3 V ≤ VLOGIC ≤ 5.5 V Unit Test Conditions/Comments
t1 33 20 ns min SCLK cycle time, write operation 65 50 ns min SCLK cycle time, read operation t2 16 10 ns min SCLK high time t3 16 10 ns min SCLK low time t4 15 10 ns min SYNC to SCLK falling edge setup time 2 2 µs max SYNC to SCLK falling edge setup time t5 7 7 ns min Data setup time t6 5 5 ns min Data hold time t7 15 10 ns min SCLK falling edge to SYNC rising edge t8 30 30 ns min Minimum SYNC high time for write operations 60 60 ns min Minimum SYNC high time for register read operations t9 0 0 ns min SYNC rising edge to next SCLK falling edge t10 56 25 ns max SCLK rising edge to SDO valid
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
003
200µA IOH
15688- Figure 2. Load Circuit for Logic Output (SDO) Timing Specifications
t1 t9 SCLK t2 t t t3 t 8 4 7 SYNC t6 t5 SDI DB15 DB0 t10
004
SDO DB15 DB0
15688- Figure 3. Timing Diagram Rev. 0 | Page 6 of 10 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Die Specifications and Assembly Recommendations Ordering Guide
