Datasheet LTM4626 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 20VIN, 12A Step-Down DC/DC µModule Regulator |
| Pages / Page | 28 / 7 — PIN FUNCTIONS RUN (B4):. PGOOD (B5):. SENSE (A6):. TSENSE (A7):. SW … |
| Revision | B |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
PIN FUNCTIONS RUN (B4):. PGOOD (B5):. SENSE (A6):. TSENSE (A7):. SW (B7):. GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7):
Model Line for this Datasheet
Text Version of Document
link to page 9 link to page 9 LTM4626
PIN FUNCTIONS RUN (B4):
Run Control Input Pin. Enable regulator opera-
PGOOD (B5):
Output Power Good Pin with Open-Drain tion by tying the specific RUN pin above 1.25V. Tying it Logic. PGOOD is pulled to ground when the voltage on the below 1.1V shuts down the specific regulator channel. FB pin is not within ±10% of the internal 0.6V reference.
T + – SENSE (A6):
Temperature Monitor Pin. An internal diode
TSENSE (A7):
Low Side of the Internal Temperature connected PNP transistor is placed between T + SENSE and Monitor. T – SENSE pins. See the Applications Information section.
SW (B7):
Switching node of each channel that is used
GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7):
for testing purposes. Also an R-C snubber network can Power Ground Pins for Both Input and Output Returns. be applied to reduce or eliminate switch node ringing, or Use large PCB copper areas to connect all GND together. otherwise leave floating. See the Applications Information section.
BLOCK DIAGRAM
PGOOD 10k INTVCC INTVCC INTVCC V 2.2µF IN VIN 3.1V TO 20V 0.1µF CIN MODE/CLKIN 10µF 25V 20k 0.24µH VOUT VOUT CLKOUT 1.5V COUT 12A 100µF POWER CONTROL 0.1µF PHMODE ×2 GND 6.3V TRACK/SS – 0.1µF VOSNS RFB RUN 40.2k VIN FB COMPa 60.4k + COMPb VOSNS INTERNAL INTERNAL FILTER COMP 274k FREQ GND 4626 BD
Figure 1. Simplified LTM4626 Block Diagram
Rev B For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts
PIN FUNCTIONS RUN (B4):
Run Control Input Pin. Enable regulator opera-
PGOOD (B5):
Output Power Good Pin with Open-Drain tion by tying the specific RUN pin above 1.25V. Tying it Logic. PGOOD is pulled to ground when the voltage on the below 1.1V shuts down the specific regulator channel. FB pin is not within ±10% of the internal 0.6V reference.
T + – SENSE (A6):
Temperature Monitor Pin. An internal diode
TSENSE (A7):
Low Side of the Internal Temperature connected PNP transistor is placed between T + SENSE and Monitor. T – SENSE pins. See the Applications Information section.
SW (B7):
Switching node of each channel that is used
GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7):
for testing purposes. Also an R-C snubber network can Power Ground Pins for Both Input and Output Returns. be applied to reduce or eliminate switch node ringing, or Use large PCB copper areas to connect all GND together. otherwise leave floating. See the Applications Information section.
BLOCK DIAGRAM
PGOOD 10k INTVCC INTVCC INTVCC V 2.2µF IN VIN 3.1V TO 20V 0.1µF CIN MODE/CLKIN 10µF 25V 20k 0.24µH VOUT VOUT CLKOUT 1.5V COUT 12A 100µF POWER CONTROL 0.1µF PHMODE ×2 GND 6.3V TRACK/SS – 0.1µF VOSNS RFB RUN 40.2k VIN FB COMPa 60.4k + COMPb VOSNS INTERNAL INTERNAL FILTER COMP 274k FREQ GND 4626 BD
Figure 1. Simplified LTM4626 Block Diagram
Rev B For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts
