Datasheet ADP150 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Ultralow Noise, 150 mA CMOS Linear Regulator |
| Pages / Page | 20 / 5 — Data Sheet. ADP150. ABSOLUTE MAXIMUM RATINGS. Table 3. Parameter. Rating. … |
| Revision | C |
| File Format / Size | PDF / 851 Kb |
| Document Language | English |
Data Sheet. ADP150. ABSOLUTE MAXIMUM RATINGS. Table 3. Parameter. Rating. THERMAL DATA. THERMAL RESISTANCE. Table 4. Thermal Resistance
Model Line for this Datasheet
- ADP150ACBZ-1.8-R7 ADP150ACBZ-2.5-R7 ADP150ACBZ-2.6-R7 ADP150ACBZ-2.75R7 ADP150ACBZ-2.8-R7 ADP150ACBZ-2.85R7 ADP150ACBZ-3.0-R7 ADP150ACBZ-3.3-R7 ADP150AUJZ-1.8-R7 ADP150AUJZ-2.0-R7 ADP150AUJZ-2.5-R7 ADP150AUJZ-2.65-R7 ADP150AUJZ-2.8-R7 ADP150AUJZ-3.0-R7 ADP150AUJZ-3.3-R7 ADP150WACBZ-1.8-R7 ADP150WACBZ-2.5-R7 ADP150WACBZ-2.6-R7 ADP150WACBZ-2.75-R7 ADP150WACBZ-2.8-R7 ADP150WACBZ-2.85-R7 ADP150WACBZ-3.0-R7 ADP150WACBZ-3.3-R7
Text Version of Document
Data Sheet ADP150 ABSOLUTE MAXIMUM RATINGS
The junction-to-ambient thermal resistance (θ
Table 3.
JA) of the package is based on modeling and a calculation using a 4-layer board.
Parameter Rating
The junction-to-ambient thermal resistance is highly dependent VIN to GND −0.3 V to +6.5 V on the application and board layout. In applications where high VOUT to GND −0.3 V to VIN maximum power dissipation exists, close attention to thermal EN to GND −0.3 V to +6.5 V board design is required. The value of θJA can vary, depending on Storage Temperature Range −65°C to +150°C PCB material, layout, and environmental conditions. The specified Operating Junction Temperature Range −40°C to +125°C values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board. Operating Ambient Temperature Range −40°C to +85°C Refer to JESD 51-7 and JESD 51-9 for detailed information Soldering Conditions JEDEC J-STD-020 on the board construction. For additional information, see Stresses above those listed under Absolute Maximum Ratings the AN-617 Application Note, MicroCSP™ Wafer Level Chip may cause permanent damage to the device. This is a stress Scale Package. rating only; functional operation of the device at these or any ΨJB is the junction-to-board thermal characterization parameter other conditions above those indicated in the operational with units of °C/W. ΨJB of the package is based on modeling and section of this specification is not implied. Exposure to absolute a calculation using a 4-layer board. The JESD51-12, Guidelines maximum rating conditions for extended periods may affect for Reporting and Using Package Thermal Information, states that device reliability. thermal characterization parameters are not the same as thermal
THERMAL DATA
resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in thermal Absolute maximum ratings apply individually only, not in resistance, θ combination. The ADP150 can be damaged when the junction JB. Therefore, ΨJB thermal paths include convection from the top of the package as wel as radiation from the package, temperature limits are exceeded. Monitoring ambient temperature factors that make Ψ does not guarantee that T JB more useful in real-world applications. J is within the specified temperature Maximum junction temperature (T limits. In applications with high power dissipation and poor J) is calculated from the board temperature (T thermal resistance, the maximum ambient temperature may B) and power dissipation (PD) by have to be derated. TJ = TB + (PD × ΨJB) In applications with moderate power dissipation and low printed Refer to JESD51-8 and JESD51-12 for more detailed information circuit board (PCB) thermal resistance, the maximum ambient about ΨJB. temperature can exceed the maximum limit as long as the junction
THERMAL RESISTANCE
temperature is within specification limits. The junction temperature (T θJA and ΨJB are specified for the worst-case conditions, that is, a J) of the device is dependent on the ambient temperature (T device soldered in a circuit board for surface-mount packages. A), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θJA).
Table 4. Thermal Resistance
Maximum junction temperature (T
Package Type θ Ψ Unit
J) is calculated from the
JA JB
ambient temperature (T 5-Lead TSOT 170 43 °C/W A) and power dissipation (PD) by T 4-Ball, 0.4 mm Pitch WLCSP 260 58 °C/W J = TA + (PD × θJA)
ESD CAUTION
Rev. C | Page 5 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITOR ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE NOTES
The junction-to-ambient thermal resistance (θ
Table 3.
JA) of the package is based on modeling and a calculation using a 4-layer board.
Parameter Rating
The junction-to-ambient thermal resistance is highly dependent VIN to GND −0.3 V to +6.5 V on the application and board layout. In applications where high VOUT to GND −0.3 V to VIN maximum power dissipation exists, close attention to thermal EN to GND −0.3 V to +6.5 V board design is required. The value of θJA can vary, depending on Storage Temperature Range −65°C to +150°C PCB material, layout, and environmental conditions. The specified Operating Junction Temperature Range −40°C to +125°C values of θJA are based on a 4-layer, 4 inch × 3 inch circuit board. Operating Ambient Temperature Range −40°C to +85°C Refer to JESD 51-7 and JESD 51-9 for detailed information Soldering Conditions JEDEC J-STD-020 on the board construction. For additional information, see Stresses above those listed under Absolute Maximum Ratings the AN-617 Application Note, MicroCSP™ Wafer Level Chip may cause permanent damage to the device. This is a stress Scale Package. rating only; functional operation of the device at these or any ΨJB is the junction-to-board thermal characterization parameter other conditions above those indicated in the operational with units of °C/W. ΨJB of the package is based on modeling and section of this specification is not implied. Exposure to absolute a calculation using a 4-layer board. The JESD51-12, Guidelines maximum rating conditions for extended periods may affect for Reporting and Using Package Thermal Information, states that device reliability. thermal characterization parameters are not the same as thermal
THERMAL DATA
resistances. ΨJB measures the component power flowing through multiple thermal paths rather than a single path as in thermal Absolute maximum ratings apply individually only, not in resistance, θ combination. The ADP150 can be damaged when the junction JB. Therefore, ΨJB thermal paths include convection from the top of the package as wel as radiation from the package, temperature limits are exceeded. Monitoring ambient temperature factors that make Ψ does not guarantee that T JB more useful in real-world applications. J is within the specified temperature Maximum junction temperature (T limits. In applications with high power dissipation and poor J) is calculated from the board temperature (T thermal resistance, the maximum ambient temperature may B) and power dissipation (PD) by have to be derated. TJ = TB + (PD × ΨJB) In applications with moderate power dissipation and low printed Refer to JESD51-8 and JESD51-12 for more detailed information circuit board (PCB) thermal resistance, the maximum ambient about ΨJB. temperature can exceed the maximum limit as long as the junction
THERMAL RESISTANCE
temperature is within specification limits. The junction temperature (T θJA and ΨJB are specified for the worst-case conditions, that is, a J) of the device is dependent on the ambient temperature (T device soldered in a circuit board for surface-mount packages. A), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θJA).
Table 4. Thermal Resistance
Maximum junction temperature (T
Package Type θ Ψ Unit
J) is calculated from the
JA JB
ambient temperature (T 5-Lead TSOT 170 43 °C/W A) and power dissipation (PD) by T 4-Ball, 0.4 mm Pitch WLCSP 260 58 °C/W J = TA + (PD × θJA)
ESD CAUTION
Rev. C | Page 5 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITOR ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE NOTES
