Datasheet AD8079 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Dual 260 MHz Gain = +2.0 & +2.2 Buffer |
| Pages / Page | 12 / 9 — AD8079. CC = 1.3pF. IN = 10dBm. OUTPUT – dB. OUT+. –10. OUT–. –12. –14. … |
| Revision | A |
| File Format / Size | PDF / 357 Kb |
| Document Language | English |
AD8079. CC = 1.3pF. IN = 10dBm. OUTPUT – dB. OUT+. –10. OUT–. –12. –14. 0.1M. 10M. 100M. FREQUENCY – Hz. Layout Considerations
Model Line for this Datasheet
Text Version of Document
AD8079
The current feedback nature of the op amps, in addition to
6
enabling the wide bandwidth, provides an output drive of more
CC = 1.3pF 4 V
than 3 V p-p into a 20 Ω load for each output at 20 MHz. On
IN = 10dBm
the other hand, the voltage feedback nature provides symmetri-
2
cal high impedance inputs and allows the use of reactive compo-
0
nents in the feedback network.
–2
The circuit consists of the two op amps each configured as a
–4
unity gain follower by the 750 Ω feedback resistors between
–6
each op amp’s output and inverting input. The output of each
OUTPUT – dB
op amp has a 750 Ω resistor to the inverting input of the other
–8 OUT+
op amp. Thus, each output drives the other op amp through a
–10 OUT–
unity gain inverter configuration. By connecting the two ampli-
–12
fiers as cross-coupled inverters, their outputs are free to be equal and opposite, assuring zero-output common-mode voltage.
–14 0.1M 1M 10M 100M 1G
With this circuit configuration, the common-mode signal of the
FREQUENCY – Hz
outputs is reduced. If one output moves slightly higher, the Figure 28. Differential Driver Frequency Response negative input to the other op amp drives its output to go
Layout Considerations
slightly lower and thus preserves the symmetry of the comple- The specified high speed performance of the AD8079 requires mentary outputs which reduces the common-mode signal. careful attention to board layout and component selection. The resulting architecture offers several advantages. First, the Proper RF design techniques and low parasitic component se- gain can be changed by changing a single resistor. Changing lection are mandatory. either RF or RG will change the gain as in an inverting op amp The PCB should have a ground plane covering all unused por-
9
circuit. For most types of differential circuits, more than one tions of the component side of the board to provide a low im- resistor must be changed to change gain and still maintain good pedance ground path. The ground plane should be removed CMR. from the area near the input pins to reduce stray capacitance. Reactive elements can be used in the feedback network. This is Chip capacitors should be used for supply bypassing (see Figure in contrast to current feedback amplifiers that restrict the use of 29). One end should be connected to the ground plane and the reactive elements in the feedback. The circuit described requires other within 1/8 in. of each power pin. An additional large about 1.3 pF of capacitance in shunt across RF in order to opti- (4.7 µF–10 µF) tantalum electrolytic capacitor should be con- mize peaking and realize a –3 dB bandwidth of more than nected in parallel, but not necessarily so close, to supply current 110 MHz. for fast, large-signal changes at the output. The peaking exhibited by the circuit is very sensitive to the Stripline design techniques should be used for long signal traces value of this capacitor. Parasitics in the board layout on the or- (greater than about 1 in.). These should be designed with a der of tenths of picofarads will influence the frequency response characteristic impedance of 50 Ω or 75 Ω and be properly termi- and the value required for the feedback capacitor, so a good lay- nated at each end. out is essential. The shunt capacitor type selection is also critical. Good micro- wave type chip capacitors with high Q were found to yield best performance. REV. A –9–
The current feedback nature of the op amps, in addition to
6
enabling the wide bandwidth, provides an output drive of more
CC = 1.3pF 4 V
than 3 V p-p into a 20 Ω load for each output at 20 MHz. On
IN = 10dBm
the other hand, the voltage feedback nature provides symmetri-
2
cal high impedance inputs and allows the use of reactive compo-
0
nents in the feedback network.
–2
The circuit consists of the two op amps each configured as a
–4
unity gain follower by the 750 Ω feedback resistors between
–6
each op amp’s output and inverting input. The output of each
OUTPUT – dB
op amp has a 750 Ω resistor to the inverting input of the other
–8 OUT+
op amp. Thus, each output drives the other op amp through a
–10 OUT–
unity gain inverter configuration. By connecting the two ampli-
–12
fiers as cross-coupled inverters, their outputs are free to be equal and opposite, assuring zero-output common-mode voltage.
–14 0.1M 1M 10M 100M 1G
With this circuit configuration, the common-mode signal of the
FREQUENCY – Hz
outputs is reduced. If one output moves slightly higher, the Figure 28. Differential Driver Frequency Response negative input to the other op amp drives its output to go
Layout Considerations
slightly lower and thus preserves the symmetry of the comple- The specified high speed performance of the AD8079 requires mentary outputs which reduces the common-mode signal. careful attention to board layout and component selection. The resulting architecture offers several advantages. First, the Proper RF design techniques and low parasitic component se- gain can be changed by changing a single resistor. Changing lection are mandatory. either RF or RG will change the gain as in an inverting op amp The PCB should have a ground plane covering all unused por-
9
circuit. For most types of differential circuits, more than one tions of the component side of the board to provide a low im- resistor must be changed to change gain and still maintain good pedance ground path. The ground plane should be removed CMR. from the area near the input pins to reduce stray capacitance. Reactive elements can be used in the feedback network. This is Chip capacitors should be used for supply bypassing (see Figure in contrast to current feedback amplifiers that restrict the use of 29). One end should be connected to the ground plane and the reactive elements in the feedback. The circuit described requires other within 1/8 in. of each power pin. An additional large about 1.3 pF of capacitance in shunt across RF in order to opti- (4.7 µF–10 µF) tantalum electrolytic capacitor should be con- mize peaking and realize a –3 dB bandwidth of more than nected in parallel, but not necessarily so close, to supply current 110 MHz. for fast, large-signal changes at the output. The peaking exhibited by the circuit is very sensitive to the Stripline design techniques should be used for long signal traces value of this capacitor. Parasitics in the board layout on the or- (greater than about 1 in.). These should be designed with a der of tenths of picofarads will influence the frequency response characteristic impedance of 50 Ω or 75 Ω and be properly termi- and the value required for the feedback capacitor, so a good lay- nated at each end. out is essential. The shunt capacitor type selection is also critical. Good micro- wave type chip capacitors with high Q were found to yield best performance. REV. A –9–
