Datasheet SAMA5D3 (Microchip) - 1800
| Manufacturer | Microchip |
| Description | Low-Power Arm Cortex -A5 Processor-Based MPU, 536 MHz, FPU, Gigabit Ethernet with IEEE 1588 plus 10/100 Ethernet, Dual CAN, AES, SHA |
| Pages / Page | 1818 / 1800 — SAMA5D3 SERIES. Change. Request. Ref. Doc. Rev. 11121C. Comments |
| File Format / Size | PDF / 30.1 Mb |
| Document Language | English |
SAMA5D3 SERIES. Change. Request. Ref. Doc. Rev. 11121C. Comments
Model Line for this Datasheet
Text Version of Document
SAMA5D3 SERIES
Change
Request
Ref. Doc. Rev.
11121C
Comments
Section 25. “Fuse Controller (FUSE)” (relocated—was previously section 51)
Minor editorial changes throughout rfo Reformatted Table 25-1 “FUSE Bit Mapping” rfo Section 25.4.2 “Fuse Programming”: rfo -in step 1, replaced “using the SWEL field” with “using the WSEL field”
-in step 5, replaced “Check the WS bit of FUSE_SRx” with “Check the WS bit of FUSE_IR”
Reformatted register description sections rfo Section 25.5.1 “Fuse Control Register”: updated field descriptions rfo “Clock Generator“ section is now a subsection of Section 27. “Power Management Controller (PMC)” rfo 2020 Microchip Technology Inc. DS60001609B-page 1801
Change
Request
Ref. Doc. Rev.
11121C
Comments
Section 25. “Fuse Controller (FUSE)” (relocated—was previously section 51)
Minor editorial changes throughout rfo Reformatted Table 25-1 “FUSE Bit Mapping” rfo Section 25.4.2 “Fuse Programming”: rfo -in step 1, replaced “using the SWEL field” with “using the WSEL field”
-in step 5, replaced “Check the WS bit of FUSE_SRx” with “Check the WS bit of FUSE_IR”
Reformatted register description sections rfo Section 25.5.1 “Fuse Control Register”: updated field descriptions rfo “Clock Generator“ section is now a subsection of Section 27. “Power Management Controller (PMC)” rfo 2020 Microchip Technology Inc. DS60001609B-page 1801
