Datasheet ADA4320-1 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | Low Distortion, DOCSIS 3.0, Upstream CATV Line Driver |
| Pages / Page | 16 / 2 — REVISION HISTORY. 10/10—Rev. 0 to Rev. A. 4/10—Revision 0: Initial Version |
| Revision | A |
| File Format / Size | PDF / 365 Kb |
| Document Language | English |
REVISION HISTORY. 10/10—Rev. 0 to Rev. A. 4/10—Revision 0: Initial Version
Model Line for this Datasheet
Text Version of Document
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REVISION HISTORY 10/10—Rev. 0 to Rev. A
Changes to Product Title ... 1 Changes to Pin 14, Description, Table 6 .. 7 Changes to Current Level and Gain Adjustment Section ... 11 Changes to Output Bias, Impedance, and Termination Section ... 12 Changes to Figure 24 .. 13 Changes to Ordering Guide .. 14
4/10—Revision 0: Initial Version
Rev. A | Page 2 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
REVISION HISTORY 10/10—Rev. 0 to Rev. A
Changes to Product Title ... 1 Changes to Pin 14, Description, Table 6 .. 7 Changes to Current Level and Gain Adjustment Section ... 11 Changes to Output Bias, Impedance, and Termination Section ... 12 Changes to Figure 24 .. 13 Changes to Ordering Guide .. 14
4/10—Revision 0: Initial Version
Rev. A | Page 2 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
