Datasheet MAX5362 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package |
| Pages / Page | 13 / 10 — Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 … |
| File Format / Size | PDF / 214 Kb |
| Document Language | English |
Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package. DAC Data. MAX5360/MAX5361/MAX5362
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Text Version of Document
Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package
option is identified by the suffix L, M, N, or P added to the part number. The address is defined as the 7 most significant bits (MSBs) sent by the master after a START condition. The address options are 0x60, 0x62, 0x64, and 0x66 (left justified with LSB set to 0). The 8th bit, typically used to define a write or read protocol, sets the device’s power mode (SHDN); the device is SDA powered down when SHDN is set to 1. During a device search routine, the MAX5360/MAX5361/MAX5362 SCL acknowledge both options (SHDN = 0 or SHDN = 1) START CONDITION STOP CONDITION but does not change its power state if a stop condition (or restart) is issued immediately. The second byte (DAC data) must be sent/received for the device to update both power mode and DAC output.
DAC Data
The 6-bit DAC data is decoded as straight binary MSB Figure 5. Start and Stop Conditions first with 1LSB = (VREF / 64) and converted into the cor- responding analog voltage as shown in Table 1. Two condition (Figure 6). The bus is then free for another subbits complete the data byte; these 2 bits should be transmission. set to zero since they are not tested to guaranteed- monotonic performance. SDA’s state is sampled, and therefore must remain sta- ble while SCL is high. Data is transmitted in 8-bit bytes. After receiving the data byte, the MAX5360/MAX5361/ Nine clock cycles are required to transfer each byte to MAX5362 acknowledge its receipt and expect a STOP the MAX5360/MAX5361/MAX5362. Release SDA during condition, at which point the DAC output is updated. the 9th clock cycle as the selected device acknowl- The devices update the output and the power mode edges the receipt of the byte, by pulling SDA low dur- only if the second byte is clocked in (SHDN = 0) or out
MAX5360/MAX5361/MAX5362
ing this time. A series resistor on the SDA line may be (SHDN = 1) of the device. When SHDN = 1, the master needed if the master’s output is forced high while the will read all ones when clocking out a data byte. The selected device acknowledges (Figure 4). MAX5360/MAX5361/MAX5362 do not drive SDA except for the acknowledge bit.
Slave Address
The MAX5360/MAX5361/MAX5362 are available with one of four preset slave addresses. Each address SLAVE ADDRESS BYTE DAC CODE SDA 0 1 1 0 0 X X SHDN ACK D6 D4 D3 D2 D1 D0 S1 S0 ACK MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 START STOP CONDITION CONDITION Figure 6. Complete Serial Transmission
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option is identified by the suffix L, M, N, or P added to the part number. The address is defined as the 7 most significant bits (MSBs) sent by the master after a START condition. The address options are 0x60, 0x62, 0x64, and 0x66 (left justified with LSB set to 0). The 8th bit, typically used to define a write or read protocol, sets the device’s power mode (SHDN); the device is SDA powered down when SHDN is set to 1. During a device search routine, the MAX5360/MAX5361/MAX5362 SCL acknowledge both options (SHDN = 0 or SHDN = 1) START CONDITION STOP CONDITION but does not change its power state if a stop condition (or restart) is issued immediately. The second byte (DAC data) must be sent/received for the device to update both power mode and DAC output.
DAC Data
The 6-bit DAC data is decoded as straight binary MSB Figure 5. Start and Stop Conditions first with 1LSB = (VREF / 64) and converted into the cor- responding analog voltage as shown in Table 1. Two condition (Figure 6). The bus is then free for another subbits complete the data byte; these 2 bits should be transmission. set to zero since they are not tested to guaranteed- monotonic performance. SDA’s state is sampled, and therefore must remain sta- ble while SCL is high. Data is transmitted in 8-bit bytes. After receiving the data byte, the MAX5360/MAX5361/ Nine clock cycles are required to transfer each byte to MAX5362 acknowledge its receipt and expect a STOP the MAX5360/MAX5361/MAX5362. Release SDA during condition, at which point the DAC output is updated. the 9th clock cycle as the selected device acknowl- The devices update the output and the power mode edges the receipt of the byte, by pulling SDA low dur- only if the second byte is clocked in (SHDN = 0) or out
MAX5360/MAX5361/MAX5362
ing this time. A series resistor on the SDA line may be (SHDN = 1) of the device. When SHDN = 1, the master needed if the master’s output is forced high while the will read all ones when clocking out a data byte. The selected device acknowledges (Figure 4). MAX5360/MAX5361/MAX5362 do not drive SDA except for the acknowledge bit.
Slave Address
The MAX5360/MAX5361/MAX5362 are available with one of four preset slave addresses. Each address SLAVE ADDRESS BYTE DAC CODE SDA 0 1 1 0 0 X X SHDN ACK D6 D4 D3 D2 D1 D0 S1 S0 ACK MSB LSB MSB LSB SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 START STOP CONDITION CONDITION Figure 6. Complete Serial Transmission
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