Datasheet Si5351 (Skyworks) - 10

Si5351A/B/C-B Table 7. Output Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Frequency Range1 FCLK 0.0025 — 200 MHz Load Capacitance CL — — 15 pF FCLK < 160 MHz, Measured 45 50 55 % at VDD/2 Duty Cycle DC FCLK > 160 MHz, Measured 40 50 60 % at VDD/2 tr 20%–80%, C — 1 1.5 ns Rise/Fall Time L = 5 pF, Default high drive strength tf — 1 1.5 ns Output High Voltage VOH VDD – 0.6 — — V CL = 5 pF Output Low Voltage VOL — — 0.6 V 16, 20-QFN, 4 outputs run- — 40 95 ps, pk-pk ning, 1 per VDDO Period Jitter2,3 JPER 10-MSOP or 20-QFN, — 70 155 ps, pk-pk all outputs running 16, 20-QFN, 4 outputs run- — 50 90 ps, pk ning, 1 per VDDO Cycle-to-Cycle Jitter2,3 JCC 10-MSOP or 20-QFN, — 70 150 ps, pk all outputs running 16, 20-QFN, 4 outputs run- — 50 95 ps, pk-pk ning, 1 per VDDO Period Jitter VCXO2,3 JPER_VCXO 10-MSOP or 20-QFN, — 70 155 ps, pk-pk all outputs running 16, 20-QFN, 4 outputs run- — 50 90 ps, pk Cycle-to-Cycle Jitter ning, 1 per VDDO VCXO2,3 JCC_VCXO 10-MSOP or 20-QFN, — 70 150 ps, pk all outputs running
Notes: 1.
Only two unique frequencies above 112.5 MHz can be simultaneously output.
2.
Measured over 10K cycles. Jitter is only specified at the default high drive strength (50 output impedance).
3.
Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world” frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock outputs of 74.25, 24.576, and 48 MHz. Eight-output 20-QFN package measured with clock outputs of 33.333, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 MHz. Four-output 16-QFN package measured with clock outputs of 33.333, 27, 28.322, and 48 MHz. 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021 Document Outline 1. Ordering Guide 2. Technical Support Resources 3. Electrical Specifications 4. Functional Description 4.1. Input Stage 4.1.1. Crystal Inputs (XA, XB) 4.1.2. External Clock Input (CLKIN) 4.1.3. Voltage Control Input (VC) 4.2. Synthesis Stages 4.3. Output Stage 4.4. Spread Spectrum 4.5. Control Pins (OEB, SSEN) 4.5.1. Output Enable (OEB) 4.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B Only 4.6. Status Pins (INTR) 5. I2C Interface 6. Configuring the Si5351 6.1. Writing a Custom Configuration to RAM 6.2. Si5351 Application Examples 6.3. Replacing Crystals and Crystal Oscillators 6.4. Replacing Crystals, Crystal Oscillators, and VCXOs 6.5. Replacing Crystals, Crystal Oscillators, and PLLs 6.6. Applying a Reference Clock at XTAL Input 6.7. HCSL Compatible Outputs 7. Design Considerations 7.1. Power Supply Decoupling/Filtering 7.2. Power Supply Sequencing 7.3. External Crystal 7.4. External Crystal Load Capacitors 7.5. Unused Pins 7.6. Trace Characteristics 8. Register Map Summary 9. Register Descriptions 10. Si5351 Pin Descriptions 10.1. Si5351A 20-pin QFN 10.2. Si5351B 20-Pin QFN 10.3. Si5351C 20-Pin QFN 10.4. Si5351A 16-Pin QFN 10.5. Si5351B 16-Pin QFN 10.6. Si5351C 16-Pin QFN 10.7. Si5351A 10-Pin MSOP 11. Ordering Information 12. Packaging 12.1. 20-pin QFN Package Outline 12.2. Land Pattern: 20-Pin QFN 12.3. 16-Pin QFN Package Outline 12.4. Land Pattern: 16-Pin QFN 12.5. 10-Pin MSOP Package Outline 12.6. Land Pattern: 10-Pin MSOP 13. Top Marking 13.1. 20-Pin QFN Top Marking 13.2. Top Marking Explanation 13.3. 16-Pin QFN Top Marking 13.4. Top Marking Explanation 13.5. 10-Pin MSOP Top Marking 13.6. Top Marking Explanation Revision History