Datasheet LMC555 (Texas Instruments) - 7

LMC555 www.ti.com
SNAS558M – FEBRUARY 2000 – REVISED JULY 2016
8 Detailed Description 8.1 Overview
The LMC555 is a CMOS version of the industry standard 555 series general-purpose timers. In addition to the standard package (SOIC, VSSSOP, and PDIP) the LMC555 is also available in a chip-sized package (8-bump DSBGA) using TI’s DSBGA package technology. The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation and supply current spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor. In the astable mode, the oscillation frequency and duty cycle are accurately set by two external resistors and one capacitor. The use of TI’s LMCMOS process extends both the frequency range and the low supply capability. The LMC555 is available in an 8-pin PDIP, SOIC, VSSOP, and 8-bump DSBGA package.
8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low-Power Dissipation
The LMC555 offers the same capability of generating accurate time delays and frequencies as the LM555 but with much lower power dissipation. A power dissipation of less than 0.2 mW can be achieved with a 1.5-V operating supply voltage and less than 1 mW with a 5-V operating supply voltage. The use of TI’s LMCMOS process allows this low supply current and voltage capability. Reduced supply current spikes during output transitions and extremely low reset, trigger and threshold currents also provide low power dissipation advantages with the LMC555. Copyright © 2000–2016, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMC555 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Low-Power Dissipation 8.3.2 Various Packages and Compatibility 8.3.3 Operates in Both Astable and Monostable Mode 8.4 Device Functional Modes 8.4.1 Monostable Operation 8.4.2 Astable Operation 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.3 Application Curve 9.3 Frequency Divider 9.3.1 Design Requirements 9.3.2 Application Curve 9.4 Pulse Width Modulator 9.4.1 Design Requirements 9.4.2 Application Curve 9.5 Pulse Position Modulator 9.5.1 Design Requirements 9.5.2 Application Curve 9.6 50% Duty Cycle Oscillator 9.6.1 Design Requirements 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Community Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information