Datasheet Texas Instruments CD74HCT00

Manufacturer	Texas Instruments
Series	CD74HCT00

High Speed CMOS Logic Quad 2-Input NAND Gates

Datasheets

PDF, 717 Kb, Revision: C, File published: Aug 21, 2003

Extract from the document

	CD74HCT00E	CD74HCT00EE4	CD74HCT00M	CD74HCT00M96	CD74HCT00M96E4	CD74HCT00M96G4	CD74HCT00ME4	CD74HCT00MG4	CD74HCT00MT
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	No	No	No

	CD74HCT00E	CD74HCT00EE4	CD74HCT00M	CD74HCT00M96	CD74HCT00M96E4	CD74HCT00M96G4	CD74HCT00ME4	CD74HCT00MG4	CD74HCT00MT
N	1	2	3	4	5	6	7	8	9
Pin	14	14	14	14	14	14	14	14	14
Package Type	N	N	D	D	D	D	D	D	D
Industry STD Term	PDIP	PDIP	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
JEDEC Code	R-PDIP-T	R-PDIP-T	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	25	25	50	2500	2500	2500	50	50	250
Carrier	TUBE	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	TUBE	TUBE	SMALL T&R
Device Marking	CD74HCT00E	CD74HCT00E	HCT00M	HCT00M	HCT00M	HCT00M	HCT00M	HCT00M	HCT00M
Width (mm)	6.35	6.35	3.91	3.91	3.91	3.91	3.91	3.91	3.91
Length (mm)	19.3	19.3	8.65	8.65	8.65	8.65	8.65	8.65	8.65
Thickness (mm)	3.9	3.9	1.58	1.58	1.58	1.58	1.58	1.58	1.58
Pitch (mm)	2.54	2.54	1.27	1.27	1.27	1.27	1.27	1.27	1.27
Max Height (mm)	5.08	5.08	1.75	1.75	1.75	1.75	1.75	1.75	1.75
Mechanical Data	Download	Download	Download	Download	Download	Download	Download	Download	Download

Parameters / Models	CD74HCT00E	CD74HCT00EE4	CD74HCT00M	CD74HCT00M96	CD74HCT00M96E4	CD74HCT00M96G4	CD74HCT00ME4	CD74HCT00MG4	CD74HCT00MT
Bits	4	4	4	4	4	4	4	4	4
F @ Nom Voltage(Max), Mhz	25	25	25	25	25	25	25	25	25
ICC @ Nom Voltage(Max), mA	0.02	0.02	0.02	0.02	0.02	0.02	0.02	0.02	0.02
Operating Temperature Range, C	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125
Output Drive (IOL/IOH)(Max), mA	4/-4	4/-4	4/-4	4/-4	4/-4	4/-4	4/-4	4/-4	4/-4
Package Group	PDIP	PDIP	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
Package Size: mm2:W x L, PKG	See datasheet (PDIP)	See datasheet (PDIP)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No	No
Technology Family	HCT	HCT	HCT	HCT	HCT	HCT	HCT	HCT	HCT
VCC(Max), V	5.5	5.5	5.5	5.5	5.5	5.5	5.5	5.5	5.5
VCC(Min), V	4.5	4.5	4.5	4.5	4.5	4.5	4.5	4.5	4.5
Voltage(Nom), V	5	5	5	5	5	5	5	5	5
tpd @ Nom Voltage(Max), ns	25	25	25	25	25	25	25	25	25

	CD74HCT00E	CD74HCT00EE4	CD74HCT00M	CD74HCT00M96	CD74HCT00M96E4	CD74HCT00M96G4	CD74HCT00ME4	CD74HCT00MG4	CD74HCT00MT
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant
Pb Free	Yes	Yes

Download
SN54/74HCT CMOS Logic Family Applications and Restrictions
PDF, 102 Kb, File published: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal

Series: CD74HCT00 (9)