Today's digital delay lines can process pulses no shorter than their delay times, and that restriction confines the devices to applications in which the duty cycle remains near 50%. A limited range of available delays (2 to 100 nsec per tap) further limits their use. Longer delay is available with one-shot multivibrators of standard digital-logic families, but those devices do not retain duty-cycle information.
|Figure 1.||Based on a precision dual comparator, this delay line generates accurate duty cycles.|
The PWM control circuit in Figure 1 can handle relatively long delays, while retaining information about the input duty cycle. The upper half of this dual-path, precision one-shot works on the input signal's rising edge. The rising edge triggers the D flip-flop, IC3A, to drive IC4A’s input low. IC4A has an open-drain output; the output therefore rises exponentially according to the single R1C1 time constant. IC1A compares the output with a dc voltage equal to 67% of VCC, producing a conveniently scaled delay equal to R1C1.
The output of comparator IC1A drives the set input of an RS latch (IC2B and IC2C). It also feeds back to the input flip-flop, thereby resetting the flip-flop in anticipation of the next rising edge. The lower half of the circuit in Figure 1 works in a similar fashion, but it triggers on the input's falling edge and drives the reset input of the RS latch. You can test the circuit with a 100-kHz input signal and a nominal delay of 1 µsec. When the input duty cycle varies from 10 to 90% (limits imposed by test equipment), the duty-cycle error is less than 0.1%.
You can obtain this performance with unmatched components. The circuit produces accurate pulse widths for pulses as narrow as 20 nsec. To ensure accuracy, the timing capacitors should be NP0 types with 5% tolerance, and the resistors should be 1% accurate. The MAX907 comparator from Maxim provides the high input impedance, high precision, and low propagation delay the circuit requires. For most applications, 74HC/HCT logic is fast enough to minimize propagation-delay errors. Note the inclusion of a NAND gate connected as an inverter, IC2A, which enhances accuracy by equalizing the propagation delays in each channel.