Datasheet AD7173-8 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC |
| Pages / Page | 64 / 4 — AD7173-8. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Test … |
| Revision | B |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD7173-8. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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AD7173-8 Data Sheet SPECIFICATIONS
AVDD1 = 3.0 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock = 2 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 1.25 31250 SPS No Missing Codes1 Excluding sinc3 filter at 31.25 kSPS 24 Bits Resolution See Table 6 Noise See Table 6 Noise Free Resolution Sinc5 + sinc1 filter (default) 31.25 kSPS, REF+ = 5 V 17.5 Bits 2.6 kSPS, REF+ = 5 V 18.4 Bits 1.25 SPS, REF+ = 5 V 24 Bits ACCURACY Integral Nonlinearity (INL) 2.5 V reference ±3 ±7.5 ppm/FSR 5 V reference ±5 ppm/FSR Offset Error2 Internal short ±40 µV Offset Drift Internal short ±350 nV/°C Offset Drift vs. Time3 ±450 nV/1000 hrs Gain Error2 25°C, AVDD1 = 5 V ±10 ±50 ppm/FSR Gain Drift vs. Temperature1 ±0.5 ±1 ppm/FSR/°C Gain Drift vs. Time3 ±3 ppm/FSR/ 1000 hrs REJECTION Power Supply Rejection AVDD1 and AVDD2, VIN = 1 V 90 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz and 60 Hz1 20 SPS ODR (post filter); 50 Hz ± 1 Hz and 120 dB 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (post filter) 71 90 dB External clock, 20 SPS ODR (post filter) 85 90 dB ANALOG INPUTS Differential Input Voltage Range ±VREF V Absolute AIN Voltage Limits1 Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Buffers Enabled AVSS AVDD1 − 1.1 V Analog Input Current Buffers Enabled Single cycle settling enabled (default) Input Current ±2 nA Input Current Drift ±25 pA/°C Buffers Disabled Input Current ±6 µA/V Input Current Drift External clock ±0.1 nA/V/°C Internal clock (±2.5% clock) ±0.5 nA/V/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor on REFOUT to AVSS Output Voltage REFOUT with respect to AVSS 2.5 V Initial Accuracy1 TA = 25°C4 −0.1 +0.1 % of V Temperature Coefficient 0°C to +105°C 3.5 81 ppm/°C −40°C to +105°C 3.5 101 ppm/°C Reference Load Current, ILOAD IL −10 +10 mA Rev. B | Page 4 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
AD7173-8 Data Sheet SPECIFICATIONS
AVDD1 = 3.0 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock = 2 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 1.25 31250 SPS No Missing Codes1 Excluding sinc3 filter at 31.25 kSPS 24 Bits Resolution See Table 6 Noise See Table 6 Noise Free Resolution Sinc5 + sinc1 filter (default) 31.25 kSPS, REF+ = 5 V 17.5 Bits 2.6 kSPS, REF+ = 5 V 18.4 Bits 1.25 SPS, REF+ = 5 V 24 Bits ACCURACY Integral Nonlinearity (INL) 2.5 V reference ±3 ±7.5 ppm/FSR 5 V reference ±5 ppm/FSR Offset Error2 Internal short ±40 µV Offset Drift Internal short ±350 nV/°C Offset Drift vs. Time3 ±450 nV/1000 hrs Gain Error2 25°C, AVDD1 = 5 V ±10 ±50 ppm/FSR Gain Drift vs. Temperature1 ±0.5 ±1 ppm/FSR/°C Gain Drift vs. Time3 ±3 ppm/FSR/ 1000 hrs REJECTION Power Supply Rejection AVDD1 and AVDD2, VIN = 1 V 90 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz and 60 Hz1 20 SPS ODR (post filter); 50 Hz ± 1 Hz and 120 dB 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (post filter) 71 90 dB External clock, 20 SPS ODR (post filter) 85 90 dB ANALOG INPUTS Differential Input Voltage Range ±VREF V Absolute AIN Voltage Limits1 Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Buffers Enabled AVSS AVDD1 − 1.1 V Analog Input Current Buffers Enabled Single cycle settling enabled (default) Input Current ±2 nA Input Current Drift ±25 pA/°C Buffers Disabled Input Current ±6 µA/V Input Current Drift External clock ±0.1 nA/V/°C Internal clock (±2.5% clock) ±0.5 nA/V/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor on REFOUT to AVSS Output Voltage REFOUT with respect to AVSS 2.5 V Initial Accuracy1 TA = 25°C4 −0.1 +0.1 % of V Temperature Coefficient 0°C to +105°C 3.5 81 ppm/°C −40°C to +105°C 3.5 101 ppm/°C Reference Load Current, ILOAD IL −10 +10 mA Rev. B | Page 4 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
